Simulation Results: rom_ctrl/32kb

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.11 %
  • code
  • 94.61 %
  • assert
  • 97.67 %
  • func
  • 99.06 %
  • block
  • 96.73 %
  • line
  • 97.22 %
  • branch
  • 94.09 %
  • toggle
  • 87.12 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.61%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.000s 136.265us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 985.065us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 4.000s 368.799us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 289.412us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 358.825us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.000s 549.436us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 4.000s 368.799us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 358.825us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 433.963us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 176.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 4.000s 1924.519us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 19.000s 1617.243us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.000s 2802.317us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.000s 126.421us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 910.771us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 910.771us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 985.065us 1 1 100.00
rom_ctrl_csr_rw 4.000s 368.799us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 358.825us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 179.568us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 985.065us 1 1 100.00
rom_ctrl_csr_rw 4.000s 368.799us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 358.825us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 179.568us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.000s 909.093us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 74.000s 883.659us 5 5 100.00
rom_ctrl_tl_intg_err 32.000s 490.027us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 74.000s 883.659us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 74.000s 883.659us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 74.000s 883.659us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 74.000s 883.659us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.000s 136.265us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.000s 136.265us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.000s 136.265us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 32.000s 490.027us 25 25 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
rom_ctrl_kmac_err_chk 7.000s 2802.317us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 66860.437us 18 20 90.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.000s 909.093us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 74.000s 883.659us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 14 20 70.00
rom_ctrl_stress_all_with_rand_reset 99.000s 8437.241us 14 20 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 2 test runs
rom_ctrl_stress_all_with_rand_reset 77724459446370308076515852097097230680097002557156784176018857054489225852435 93
UVM_INFO @ 3288938796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 73218721238777448214713419566965134704057222065210011753758239140689623674327 91
UVM_INFO @ 281565955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 2 test runs
rom_ctrl_stress_all_with_rand_reset 89099023081721408037276483879621336062437969538747730605652281892115614295873 89
UVM_INFO @ 1034939925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 101499844285143451532386500778221244246322055085598629092403492546063151137554 127
UVM_INFO @ 1443109855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 30399908439625257434188630501865875181059022025023585593712745209211074203466 87
UVM_INFO @ 346193103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 36953589350524251480643984619044502249218596078594720805348764159361095660061 93
UVM_INFO @ 623661463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rom_ctrl_common_vseq] Check failed (vseq_done) 1 test run
rom_ctrl_stress_all_with_rand_reset 78082500211705163595773549294947385888621775784649554035752647140605401042144 124
UVM_INFO @ 1913203247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
rom_ctrl_stress_all_with_rand_reset 4113380207222192297672279543806751765527216996928601034306995295845924011964 92
UVM_INFO @ 1506462885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---