Simulation Results: rom_ctrl/64kb

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.19 %
  • code
  • 94.62 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 96.73 %
  • line
  • 97.22 %
  • branch
  • 94.09 %
  • toggle
  • 87.16 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.59%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 8.000s 216.731us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.000s 2428.865us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 9.000s 401.076us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 1069.148us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 9.000s 544.589us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 12.000s 4127.185us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 9.000s 401.076us 5 5 100.00
rom_ctrl_csr_aliasing 9.000s 544.589us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.000s 210.409us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.000s 298.738us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 9.000s 407.062us 2 2 100.00
stress_all 19 20 95.00
rom_ctrl_stress_all 32.000s 27058.948us 19 20 95.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 10.000s 1035.131us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 8.000s 297.653us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 13.000s 1071.646us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 13.000s 1071.646us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 9.000s 2428.865us 1 1 100.00
rom_ctrl_csr_rw 9.000s 401.076us 5 5 100.00
rom_ctrl_csr_aliasing 9.000s 544.589us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 771.759us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 9.000s 2428.865us 1 1 100.00
rom_ctrl_csr_rw 9.000s 401.076us 5 5 100.00
rom_ctrl_csr_aliasing 9.000s 544.589us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 771.759us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 37.000s 18557.226us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 267.000s 12450.567us 5 5 100.00
rom_ctrl_tl_intg_err 70.000s 5421.135us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 267.000s 12450.567us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 267.000s 12450.567us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 267.000s 12450.567us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 267.000s 12450.567us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 8.000s 216.731us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 8.000s 216.731us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 8.000s 216.731us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 70.000s 5421.135us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
rom_ctrl_kmac_err_chk 10.000s 1035.131us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 195.000s 53882.789us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 37.000s 18557.226us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 267.000s 12450.567us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 88.000s 4849.613us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all 107254196670890521530237243618267060031916792718710267486409763689210989995033 87
UVM_INFO @ 251465924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---