Simulation Results

Simulation Results: rv_dm/use_dmi_interface

06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.49 %

code
83.68 %

assert
96.90 %

func
96.90 %

block
92.96 %

line
93.77 %

branch
80.89 %

toggle
79.71 %

FSM
80.36 %

Validation stages

V1		97.69%
V2		43.33%
V2S		100.00%
V3		0.00%
unmapped		0.00%

127/130 passed

97.69 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	51.000s	3946.727us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	46.000s	988.080us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	48.000s	313.962us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	77.000s	20816.647us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	47.000s	1122.225us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	69.000s	14176.772us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	64.000s	7336.581us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	130.000s	46654.600us	20	20	100.00
jtag_dmi_csr_aliasing				4	5	80.00
	rv_dm_jtag_dmi_csr_aliasing	125.000s	300000.000us	4	5	80.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	41.000s	997.097us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	41.000s	1032.404us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	35.000s	185.835us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	42.000s	494.662us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	42.000s	128.040us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	35.000s	135.130us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	40.000s	160.252us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	47.000s	549.380us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	41.000s	997.097us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	42.000s	194.507us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	46.000s	1271.832us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	35.000s	185.835us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	47.000s	149.124us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	44.000s	847.168us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	42.000s	73.554us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	72.000s	6095.193us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	58.000s	18912.891us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	48.000s	284.150us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	58.000s	18912.891us	1	1	100.00
	rv_dm_csr_rw	42.000s	73.554us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	40.000s	39.920us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	38.000s	37.055us	1	1	100.00

78/180 passed

43.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	51.000s	3946.727us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	46.000s	1045.102us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	47.000s	376.759us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	43.000s	261.607us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	40.000s	2812.703us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	59.000s	9273.055us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	51.000s	60.862us	0	20	0.00
bad_sba				2	20	10.00
	rv_dm_bad_sba_tl_access	53.000s	11477.389us	2	20	10.00
sba_autoincrement				0	20	0.00
	rv_dm_autoincr_sba_tl_access	109.000s	31414.974us	0	20	0.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	50.000s	474.169us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	42.000s	683.616us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	40.000s	910.074us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	51.000s	35.896us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	44.000s	3632.669us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	119.000s	20598.950us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	38.000s	87.476us	1	1	100.00
stress_all				3	20	15.00
	rv_dm_stress_all	10801.000s	0.000us	3	20	15.00
alert_test				10	10	100.00
	rv_dm_alert_test	43.000s	125.268us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	46.000s	247.902us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	46.000s	247.902us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	58.000s	18912.891us	1	1	100.00
	rv_dm_csr_hw_reset	44.000s	847.168us	1	1	100.00
	rv_dm_csr_rw	42.000s	73.554us	5	5	100.00
	rv_dm_same_csr_outstanding	48.000s	610.690us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	58.000s	18912.891us	1	1	100.00
	rv_dm_csr_hw_reset	44.000s	847.168us	1	1	100.00
	rv_dm_csr_rw	42.000s	73.554us	5	5	100.00
	rv_dm_same_csr_outstanding	48.000s	610.690us	5	5	100.00

V2S

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	44.000s	1321.217us	5	5	100.00
	rv_dm_tl_intg_err	62.000s	4065.564us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	62.000s	4065.564us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	42.000s	683.616us	2	2	100.00
	rv_dm_debug_disabled	42.000s	39.608us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	42.000s	683.616us	2	2	100.00
	rv_dm_debug_disabled	42.000s	39.608us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	51.000s	3946.727us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				10	10	100.00
	rv_dm_buffered_enable	50.000s	276.980us	10	10	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	41.000s	224.500us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	41.000s	224.500us	4	4	100.00
sec_cm_exec_ctrl_mubi				10	10	100.00
	rv_dm_buffered_enable	50.000s	276.980us	10	10	100.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	20	0.00
	rv_dm_stress_all_with_rand_reset	80.000s	7793.074us	0	20	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	406.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				40 test runs
	rv_dm_delayed_resp_sba_tl_access	29994980309155569012130007663654677546365253618659895758881025868143287178055	107	UVM_INFO @ 264955125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	76996476672769413877444488252781036566491985166982184371409158151165471263087	107	UVM_INFO @ 55179009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	7153223248364834124394974683922212862695593270680711543608778681457123350472	107	UVM_INFO @ 666826770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	29501735114571722169489367664842928072807988829220067159531386712459008116881	107	UVM_INFO @ 439275974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	51348069476068462611172821952191946871028683237829444001329044984629687460010	107	UVM_INFO @ 291980798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	56997852592881085020680630216619971194220450297989361676590119844290011832268	107	UVM_INFO @ 387804105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	19331084049568117186953309579178987427113793553127979014153232849125522173315	107	UVM_INFO @ 126205721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	54980221643906870278130404940691225036076407470711440609684616587762634653059	107	UVM_INFO @ 185801511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	55210991297768905027270392920574054276355722383508072667117523749998494853684	107	UVM_INFO @ 302026540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	67104344679989549863940273462999184049534905514313967887276171346819532147386	107	UVM_INFO @ 1089555289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	30118135344243998576180047421104455812658782559273151279213415047565512245286	107	UVM_INFO @ 60861743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	114059870246272540371211970174629796964792413936129420819255636183767361380659	107	UVM_INFO @ 256447761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	74588018679758915153207262898631635856464476008873187929742585822258374271877	107	UVM_INFO @ 393732998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	101657787461032337834965479865488158609456135293959770103078135090064266565651	107	UVM_INFO @ 1288438785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	83516652470040840783839225502024352838434072126559372078468198577506968880967	107	UVM_INFO @ 50733432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	4436645142711921221520555953948614807206027534597430393965405309214106801828	107	UVM_INFO @ 372047575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	43951013491705804698674834324212756365869005704211574557896684444775469926609	107	UVM_INFO @ 120716085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	66418493709386067906398926141345183061661532399320854939964384360435797513283	107	UVM_INFO @ 145599440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	52154115167675228634829431661312062531148036175781217670172927148162500913519	107	UVM_INFO @ 418648915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	55529656839143530200588778332110191802720540563081809379554790433189466993613	107	UVM_INFO @ 194840752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	47620121693796966393160415148319626172121272831241600197675059642372903351699	107	UVM_INFO @ 64775984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	25286094161673089302025679040396174281259394065501015088219930056504197029237	107	UVM_INFO @ 86696705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	47334056370970083544220283066174777852800699951846073374030762727394610990259	107	UVM_INFO @ 297764044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	88054076578870701632134442408495080567781667363452251053366981490215567771337	107	UVM_INFO @ 401293912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	91030960664203501183745834819387652970719959053830105015128803960954119533759	107	UVM_INFO @ 103565895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	44758388416573439311910913260189752198546039582938706462555601380414778632500	107	UVM_INFO @ 1274622776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	19420170094974324975225032969998095730192456613296359688524546571802194017762	107	UVM_INFO @ 311593429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	98073704834184290615585801150348344275655214542127572231588748161879732969522	107	UVM_INFO @ 96034427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	97403761205343919247178069899445597462706065504899138072749727872608213339819	134	UVM_INFO @ 9715856708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	34967724560385080218504140633436944761133258346123158794879717921428149154079	107	UVM_INFO @ 68494992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	49564145905656314012295395432041096919497760077392954072976764479335415047765	107	UVM_INFO @ 1105995841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	54956718109468202772635535565306189243521906876792029611086200428972671713849	107	UVM_INFO @ 124919258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	15434844002424787087439692031152844499051483424792504776829036296807480287327	107	UVM_INFO @ 73520341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	91669539148904372369605484088622321274228680814687067858455264185282973976996	107	UVM_INFO @ 151001756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	5143961978527641627048331589932017330876717811041613071378868127144399363679	107	UVM_INFO @ 1319578195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	17912127096778998265526707501926872113205359639084248035405221666211645601136	107	UVM_INFO @ 451178625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	111318422914136602475885005344402395503172479540196018616927840643271541743993	107	UVM_INFO @ 206884711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	92992288465253695097292263125947989083450600372162132300123794989279763772242	107	UVM_INFO @ 103256010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	88960936716498446135978369873848754864941767938005509654722138608573713454569	107	UVM_INFO @ 339186727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	67109555378135811457943076719357447313299739792935248385622706639882088256073	107	UVM_INFO @ 48102318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				38 test runs
	rv_dm_sba_tl_access	58884960554767481891539304140015544447044464996411994887431030952394308992595	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23823
	rv_dm_autoincr_sba_tl_access	72798696856666999727682522001337029493759721886615794588593323528593074409327	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23777
	rv_dm_sba_tl_access	16729398956126055211192116338151545769791656920922918556280959693394559015071	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23781
	rv_dm_bad_sba_tl_access	10026006906612650869932471542366244362434425713526996626126533952234425454927	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23887
	rv_dm_autoincr_sba_tl_access	4114663532990439623198863260147066720542886505693356371944789239709468756065	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_sba_tl_access	78456149839252465248470522814739780212940791358753532457971337531938638986227	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23726
	rv_dm_bad_sba_tl_access	57675125564373834888509247977956396722900719003424930865885472480430886426479	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10311
	rv_dm_sba_tl_access	63014507700665141057922063214930691051793522182034020526403871518247620370441	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23874
	rv_dm_bad_sba_tl_access	32523278409416605864669760391913413077431934758725549081511735892290290894612	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23824
	rv_dm_sba_tl_access	15830453653684341903899610552638477040009582743754090554205863620883431173741	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23862
	rv_dm_sba_tl_access	47068487858928290726254475380830219909480307735253907461350957625595122374923	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23859
	rv_dm_bad_sba_tl_access	8152102718672281537191249850377062399946090788647630959156683844543449836403	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23756
	rv_dm_sba_tl_access	85636875470002384756498235872567394213616203616003225057854401752268451739415	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23726
	rv_dm_sba_tl_access	113309568474755815028976390779129464694723730240329351991782539339718404911891	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23789
	rv_dm_sba_tl_access	96699726904931593459741326474939240353402676343933513924016623765703694804738	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23822
	rv_dm_autoincr_sba_tl_access	20322476113863673617065855235371988675748687104589950985572712091901468622100	153	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23973
	rv_dm_sba_tl_access	34349594373657452889304216891024201036682927056424420313822487743088455168877	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23865
	rv_dm_bad_sba_tl_access	9283500672118589497293201825576575262588224555581309390323034806967148015727	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24058
	rv_dm_sba_tl_access	24257437091390380527666784717135625773821438114808055899499297138091324632537	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23723
	rv_dm_sba_tl_access	78950910543129400721755618191826660046896422283873041986113045241239956716360	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23812
	rv_dm_sba_tl_access	53933721550152611359467186906399631469091663567448231190622551567257168892850	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23721
	rv_dm_autoincr_sba_tl_access	98371546725963986727854056666490459270102387350670223730244380520713929646694	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23816
	rv_dm_sba_tl_access	97970144085956791503211730828516379894610614995827527614210238833431695877438	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23855
	rv_dm_bad_sba_tl_access	113895390837861929889955585272213455001036267891688791789477528987498114308358	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23767
	rv_dm_autoincr_sba_tl_access	25285682789473833662816226406333717572258596120687991172135170305108176781454	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_sba_tl_access	45107828678626166012630504430577008467054568991767835321130433876135288351814	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23877
	rv_dm_autoincr_sba_tl_access	62556337085522835855839915848204144493765557857902298204107484300161575868259	129	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23907
	rv_dm_sba_tl_access	4587521532491930960125475851190797959958673619769807506395150061639287629850	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
	rv_dm_bad_sba_tl_access	63564725824919750973817049585042313258375470001408507722782102741555112434898	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24139
	rv_dm_sba_tl_access	60881208350443653707543151609491280398407569488118433116142262820197614741777	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23786
	rv_dm_bad_sba_tl_access	74259434866924233919678896790640752044240904700856906295916960307092354136263	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23951
	rv_dm_sba_tl_access	84350574922271435620536892589071101928805876096331052187280092145260103351860	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23857
	rv_dm_autoincr_sba_tl_access	19086722675240831184948892105718875112832119629980329050484411487025086589789	129	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10110
	rv_dm_sba_tl_access	68533588092483993223142555699063462656299793922927400980798537406394950413968	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23883
	rv_dm_bad_sba_tl_access	53500171976868755598446844873014167069234451333398892522681346722561604046000	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23971
	rv_dm_autoincr_sba_tl_access	97931539747878900505509516095321320653460778469315354156462976788684535627114	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10311
	rv_dm_sba_tl_access	1950238368152709238211958420924575725956455732114127461486863182347540130611	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23814
	rv_dm_bad_sba_tl_access	51924853474747830355168088918757330946549741494702006902420816019523440323702	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23859
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				14 test runs
	rv_dm_mem_tl_access_resuming	107121145302768214136764126745091816098315089313530832272308702106389187272276	87	UVM_INFO @ 494661759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	69911639873868171955212745030203393839069937519761295622638047710290176708649	99	UVM_INFO @ 294741686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	68728878403774364404717979835938912854583301302180601467755307409926559778587	87	UVM_INFO @ 433018216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	79955378871858681367969514287804085148150360281047885853154660932909335580682	88	UVM_INFO @ 120927517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	20675081053049864255199067865806021052317809408234151610388297573853417759235	105	UVM_INFO @ 435422222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	58348265841023940125331562319836732759072790834342686821514226078042957322918	91	UVM_INFO @ 143219385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	10451705633276656602036944064159096713111188439843204295236118095027102514981	109	UVM_INFO @ 1240980343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	78711619719793469114869343264988738039319200636354823251227499067729374316636	90	UVM_INFO @ 2743295311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	70614194883480396532569802299594002060963312404156460713235650483312539743285	126	UVM_INFO @ 1520215629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	41258757904215602400291047086895716007961342231209859698626910437997065477215	97	UVM_INFO @ 206490124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	92000525899860572509849800056715427085422932577925661146846423121369046871341	92	UVM_INFO @ 269189400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	33982100066829795042140580282540670489983967818938649199022793226871992870864	88	UVM_INFO @ 201681229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	78879895718267710482175940592524182245379715913886925163499221824237504554980	104	UVM_INFO @ 1168382250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	63414140217120355269403482267922844516170316594745586793967291805554022529421	94	UVM_INFO @ 5804013394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				10 test runs
	rv_dm_hart_unavail	41147439684431527822026644593447011529865311825961018169873442774222184972253	87	UVM_INFO @ 86894441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	6882961740184109259680923409891530366063880487590305758294134897554791122571	87	UVM_INFO @ 39480908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	72627705496949131689635061754624274034441777262861816438801658057461744816701	87	UVM_INFO @ 35896176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	1408050218036149178552632824307928685011816156048392477682302246482097727832	87	UVM_INFO @ 122321738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	40013706586345105074371352863797964504653587622715725100812417915622886717941	87	UVM_INFO @ 48053735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	112175040005976353100764221632158740491665708056284576687113906559058936171030	91	UVM_INFO @ 364451653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	85430913638403183539794924129512364560807618378595299837554305186177250778275	88	UVM_INFO @ 287088037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	63823685698734663361896787997991163017134980257252439118835772926247213356139	93	UVM_INFO @ 6238368719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	83930141653101284703010681425750040500457686960126583684965917380757283288999	88	UVM_INFO @ 138215984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	105960730004627330492199921009206532202061905664047188992172843936679388285818	102	UVM_INFO @ 1705190916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				9 test runs
	rv_dm_jtag_dmi_debug_disabled	41759683901681234248714593063607504127592710091751971989526750688570018185260	87	UVM_INFO @ 123960187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	57867888388108560503763485510909065694836669486221762195159853784297247235432	87	UVM_INFO @ 474169376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	111603707729954866962179009441098722287222199700616134635873771331853493694375	91	UVM_INFO @ 139730850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	37064227080521562774282439290874837161044231030966617671064151850200315759731	92	UVM_INFO @ 413250963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	28051829860805962269089758299916951497654701688503058261191538448061969986079	91	UVM_INFO @ 138336687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	5185330086991945538681083697682227596817032224583163320837524023017078261295	93	UVM_INFO @ 4664431172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	50222366573134573840917175108522831486068282739103723483194614270980132408480	95	UVM_INFO @ 459238550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	27173160956045043620802558396137031675909310795406066212646422730295319715508	89	UVM_INFO @ 516458771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	106057230869344480482852257626419201505829375800430915025359998747242729410702	95	UVM_INFO @ 1377800391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				6 test runs
	rv_dm_jtag_dmi_csr_aliasing	111518011676008428834414396961929449239242654557804985477190521686698052228293	89	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	97946151545136435559895593331579389221158032124432239045996262412833308401800	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	44778735410715765848602621080828119560577823460782933105155254606006358825079	92	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	79356553820595908599491175337961552361261987792244060269008084595757529418564	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	57068914429354529119410119802675342085211935898745061321654304637326358795656	89	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	93017884664447804658255520971305418166806645723031226085773656350502802838788	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				5 test runs
	rv_dm_stress_all_with_rand_reset	64321267866834806412421529762284555298885881413333459023404819726584206813171	132	UVM_INFO @ 7793074277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	97394108578831585899529265621096280178655503192428645352379804693223710666987	115	UVM_INFO @ 1070683816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	104082639297818887240643451416256450862510536607390458574470803548388741050814	94	UVM_INFO @ 726938421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	83557177167271650360037740692953623947499905566292187437425278381996312526886	101	UVM_INFO @ 1914920727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	14055666065975496702647380416096896405755123054788927243571299920103544288711	115	UVM_INFO @ 2862607236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				4 test runs
	rv_dm_stress_all	64468132919339410015337943220194477309660216631543947426017584419194287236430	None
	rv_dm_stress_all	91754061798040513494226209462486191129412466897412861600720186231016676024419	None
	rv_dm_stress_all	21850811199333070418127335943004910515589385875869136269031802203295206436333	None
	rv_dm_stress_all	36872994884132364727113277648692381516390643006229239527610167430674578135846	None