Simulation Results: rv_timer

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
85.04%
V2S
100.00%
V3
37.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 534.016us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 14.125us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 1.000s 14.196us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 61.663us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 72.182us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 496.400us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 1.000s 14.196us 5 5 100.00
rv_timer_csr_aliasing 1.000s 72.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 20 5.00
rv_timer_random_reset 9.000s 7920.163us 1 20 5.00
disabled 20 20 100.00
rv_timer_disabled 6.000s 2329.662us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 455.000s 318402.490us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 455.000s 318402.490us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 9.000s 5596.405us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 13.592us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 14.352us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 325.376us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 325.376us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 14.125us 1 1 100.00
rv_timer_csr_rw 1.000s 14.196us 5 5 100.00
rv_timer_csr_aliasing 1.000s 72.182us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 67.285us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 14.125us 1 1 100.00
rv_timer_csr_rw 1.000s 14.196us 5 5 100.00
rv_timer_csr_aliasing 1.000s 72.182us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 67.285us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.000s 65.444us 5 5 100.00
rv_timer_tl_intg_err 2.000s 1649.543us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 1649.543us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 2.000s 265.672us 2 10 20.00
max_value 0 10 0.00
rv_timer_max 3.000s 175.556us 0 10 0.00
stress_all_with_rand_reset 13 20 65.00
rv_timer_stress_all_with_rand_reset 51.000s 6933.847us 13 20 65.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 27 test runs
rv_timer_min 10446445079681335171296515696837856423915338410267233103187419531233059707688 86
UVM_INFO @ 239945086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 26723268081490083854007232297158617954153973632542708795106818571750253032447 84
UVM_INFO @ 118095771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 94183256130755149849399801908718715983574575816105891951443144001201945263144 84
UVM_INFO @ 292478076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 99617420883437007962313583479388231329506818781382594792107281773927970154600 85
UVM_INFO @ 64798702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 6177169517293894519604119439674082186591383226797438464837386131601628776722 84
UVM_INFO @ 617666242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 23965877527774573694670909761665107069944307616810445901777863512160375610886 84
UVM_INFO @ 125137187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 88304207921330976093429839968515577747751522223312834837362449009773218642899 85
UVM_INFO @ 597153336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 94242771100186548108863244781942780308768159360639013681674316781852426823388 84
UVM_INFO @ 56587330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 14608559033600915306262223427919557143003884643202526845769907195520442999981 84
UVM_INFO @ 81356107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 73118045568621304426219271063805057419798459324422744940250654537912746476952 84
UVM_INFO @ 75634521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 26851136617459552725396273424566367523294506079987707423360485001875205776336 84
UVM_INFO @ 658491559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 47142054780362975654040689079282118855904164481345596231965707700617942349416 84
UVM_INFO @ 53810072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 71024991543502146053367360324068235793364303134205800404727058206603596361984 85
UVM_INFO @ 354279839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 45126115043284527975126446648745368133214436401287286302210186347669066811772 85
UVM_INFO @ 65555019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 86748099530373636223885353486015572486017850802911301053786320828155620445251 84
UVM_INFO @ 194135414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 29753247298585172688193301919908764959693515016773729974276607718030198370777 84
UVM_INFO @ 56676487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 37133633376173779755106564464167556176126704431707539539710536040000851456619 84
UVM_INFO @ 199961258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 51682745927467543545201810269338787549973398588567772939350672008138620578846 84
UVM_INFO @ 251636795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 57693417760202470631147401339135470951453080335547251839863154343113393424083 84
UVM_INFO @ 557707881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 103612533896632561105250795837126376436134591992111544961536665050990991333871 84
UVM_INFO @ 254390996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 26459954896656969823399943826905731389597824438045349369753385429213446685056 84
UVM_INFO @ 446869932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 8028233588901740229734842859572517106747112705935812743386733016467903295891 86
UVM_INFO @ 7920162530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 2050116065121706992719680397691232354314250606115257498584659901353524504399 84
UVM_INFO @ 345107361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 13081877898637069082958559995301457473523633798224683585307223479489623275564 84
UVM_INFO @ 81491630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 96837559463663157820057429044836670816342442826749338813306785333726138599766 84
UVM_INFO @ 426751302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 50929799440868679281295168019268699497989627555780233399626332449742076641695 84
UVM_INFO @ 235700251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 7079414599887290934311480416330378242275817554817986458086581791309564807129 84
UVM_INFO @ 164768918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 91814646071950724020065921349986720224314240023636918313895673941404269992003 84
UVM_INFO @ 175555875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 27257231318179499735586438722289848553491982296239904871352849045560167499206 84
UVM_INFO @ 43505650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 35927642058809037176587789927084838224667723833916217821892584151401863628704 84
UVM_INFO @ 124816410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 79057574047108250915710708120119330088859434183477989147130464619631618079852 84
UVM_INFO @ 44467145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 40064740551081482993500337724373432952503640769468444438120025568825464318439 84
UVM_INFO @ 176253031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 19972851208284747572133272613019233928222691435989761367920416024177287314153 84
UVM_INFO @ 64607004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 53158955916556057914640098296863375217468479963725470323706676476556846204398 84
UVM_INFO @ 169668396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 31357499163881533524904897442597476829178853002922104952688610539014024559511 84
UVM_INFO @ 85469277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 65166523238910212674940906066511564170687319575770241823180808614587658280416 84
UVM_INFO @ 53509105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 4 test runs
rv_timer_stress_all_with_rand_reset 56090719382457194397821907069672079827676663635279428968685151006982580029874 344
UVM_INFO @ 16663423474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 90757560404425573830489057043663157462059022739558808927120198105468902264043 321
UVM_INFO @ 57129254491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 85893774502166608052514629543719900886916673901764043947238654032514288346066 183
UVM_INFO @ 32053833097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 45622152234734440643908019896605316739432420205445474019171612349469071680021 150
UVM_INFO @ 851857889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
rv_timer_stress_all_with_rand_reset 104759358163231849536183021959107086129912381801194120655217913765165194237 120
UVM_INFO @ 4075359697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 52797161373105650227075254553027817490176909231044011165020872545411763424252 178
UVM_INFO @ 1236452833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 25141166190915863218950160749201281016488724399282374478118603218998168155983 213
UVM_INFO @ 4081046892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 16576551922571628458494065761610840982855354892134087818790923085109830247004 85
UVM_INFO @ 44087436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---