Simulation Results: spi_host

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.13 %
  • code
  • 95.03 %
  • assert
  • 96.59 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.90%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 66.000s 6134.480us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 43.222us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 44.719us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 454.087us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 42.259us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 18.649us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 44.719us 5 5 100.00
spi_host_csr_aliasing 2.000s 42.259us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 43.207us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 22.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 61.207us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 45.000s 2046.015us 10 10 100.00
spi_host_error_cmd 2.000s 20.606us 10 10 100.00
spi_host_event 97.000s 3027.276us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 238.278us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 238.278us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 238.278us 10 10 100.00
upper_range_clkdiv 3 5 60.00
spi_host_upper_range_clkdiv 705.000s 67690.162us 3 5 60.00
sw_reset 10 10 100.00
spi_host_sw_reset 11.000s 495.379us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 50.863us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 238.278us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 238.278us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 66.000s 6134.480us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 66.000s 6134.480us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 28.000s 1840.533us 10 10 100.00
spien 10 10 100.00
spi_host_spien 32.000s 938.593us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 147.000s 50178.400us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 3.000s 176.056us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 45.000s 2046.015us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 35.487us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 58.860us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 398.568us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 398.568us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 43.222us 1 1 100.00
spi_host_csr_rw 2.000s 44.719us 5 5 100.00
spi_host_csr_aliasing 2.000s 42.259us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 77.488us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 43.222us 1 1 100.00
spi_host_csr_rw 2.000s 44.719us 5 5 100.00
spi_host_csr_aliasing 2.000s 42.259us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 77.488us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 917.781us 25 25 100.00
spi_host_sec_cm 2.000s 400.617us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 917.781us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
spi_host_upper_range_clkdiv 37096323320959238033073210428750683228167004965120222370014798720708815156735 115
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_upper_range_clkdiv 13185731426268289650324066783027523348523988962751906600022622429263162287486 151
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---