Simulation Results: ac_range_check

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
92.45%
V2
98.86%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 17 20 85.00
ac_range_check_smoke 49.000s 26334.484us 17 20 85.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 73.000s 2589.490us 19 20 95.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 69.908us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 187.977us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 30.000s 8812.693us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 30.000s 5441.305us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 38.904us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 187.977us 5 5 100.00
ac_range_check_csr_aliasing 30.000s 5441.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 62.561us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 61.000s 1470.504us 1 1 100.00
stress_all 9 10 90.00
ac_range_check_stress_all 324.000s 56957.016us 9 10 90.00
alert_test 10 10 100.00
ac_range_check_alert_test 28.000s 17.107us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 13.676us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 5.000s 129.447us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 5.000s 129.447us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 69.908us 1 1 100.00
ac_range_check_csr_rw 3.000s 187.977us 5 5 100.00
ac_range_check_csr_aliasing 30.000s 5441.305us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 369.919us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 69.908us 1 1 100.00
ac_range_check_csr_rw 3.000s 187.977us 5 5 100.00
ac_range_check_csr_aliasing 30.000s 5441.305us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 369.919us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 4452.284us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 4452.284us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 4452.284us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 4452.284us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 139.000s 22173.802us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 75.608us 5 5 100.00
ac_range_check_tl_intg_err 15.000s 819.708us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 368.000s 21810.159us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 50.000s 6301.710us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 5 test runs
ac_range_check_smoke 23853611519578114317345631750613725307718756839400129857317573477364067039952 4680
UVM_INFO @ 33524705376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 12997594602877026358521267204991404665237109378617610944494048856472780995943 4332
UVM_INFO @ 8458695897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 30997511341908828115942561676552469651972644313854105857486616737477686066909 9530
UVM_INFO @ 2923067948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 26702833978722313479049728594225347352831019032263228532037645524498126460714 4082
UVM_INFO @ 1726905804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 25290077487427964721040149607277049024654746284683650203081399559784278098389 4500
UVM_INFO @ 524725353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---