Simulation Results

Simulation Results: clkmgr

12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
83.62 %

code
79.89 %

assert
94.01 %

func
76.96 %

line
91.54 %

branch
94.43 %

cond
88.48 %

toggle
100.00 %

FSM
25.00 %

Validation stages

V1		65.22%
V2		68.38%
V2S		30.48%
V3		5.00%

15/23 passed

65.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.060s	73.724us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.170s	17.395us	1	1	100.00
csr_rw				2	5	40.00
	clkmgr_csr_rw	1.640s	52.129us	2	5	40.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	2.420s	114.243us	0	1	0.00
csr_aliasing				0	1	0.00
	clkmgr_csr_aliasing	1.310s	24.887us	0	1	0.00
csr_mem_rw_with_rand_reset				2	5	40.00
	clkmgr_csr_mem_rw_with_rand_reset	2.480s	34.552us	2	5	40.00
regwen_csr_and_corresponding_lockable_csr				2	6	33.33
	clkmgr_csr_rw	1.640s	52.129us	2	5	40.00
	clkmgr_csr_aliasing	1.310s	24.887us	0	1	0.00

80/117 passed

68.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	2.090s	150.807us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	2.910s	157.663us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.920s	79.622us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.060s	73.724us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.160s	15.651us	0	10	0.00
frequency_timeout				1	10	10.00
	clkmgr_frequency_timeout	1.140s	14.138us	1	10	10.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.160s	15.651us	0	10	0.00
stress_all				1	10	10.00
	clkmgr_stress_all	3.530s	173.591us	1	10	10.00
alert_test				10	10	100.00
	clkmgr_alert_test	2.380s	103.649us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	17.000s	1848.260us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	17.000s	1848.260us	25	25	100.00
tl_d_outstanding_access				3	12	25.00
	clkmgr_csr_hw_reset	1.170s	17.395us	1	1	100.00
	clkmgr_csr_rw	1.640s	52.129us	2	5	40.00
	clkmgr_csr_aliasing	1.310s	24.887us	0	1	0.00
	clkmgr_same_csr_outstanding	1.340s	28.836us	0	5	0.00
tl_d_partial_access				3	12	25.00
	clkmgr_csr_hw_reset	1.170s	17.395us	1	1	100.00
	clkmgr_csr_rw	1.640s	52.129us	2	5	40.00
	clkmgr_csr_aliasing	1.310s	24.887us	0	1	0.00
	clkmgr_same_csr_outstanding	1.340s	28.836us	0	5	0.00

V2S

32/105 passed

30.48 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	30	6.67
	clkmgr_sec_cm	125.830s	10181.287us	2	5	40.00
	clkmgr_tl_intg_err	94.460s	10018.466us	0	25	0.00
shadow_reg_update_error				17	20	85.00
	clkmgr_shadow_reg_errors	2284.570s	200000.000us	17	20	85.00
shadow_reg_read_clear_staged_value				17	20	85.00
	clkmgr_shadow_reg_errors	2284.570s	200000.000us	17	20	85.00
shadow_reg_storage_error				17	20	85.00
	clkmgr_shadow_reg_errors	2284.570s	200000.000us	17	20	85.00
shadowed_reset_glitch				17	20	85.00
	clkmgr_shadow_reg_errors	2284.570s	200000.000us	17	20	85.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.260s	18.893us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	94.460s	10018.466us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.160s	15.651us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				1	10	10.00
	clkmgr_frequency_timeout	1.140s	14.138us	1	10	10.00
sec_cm_meas_config_shadow				17	20	85.00
	clkmgr_shadow_reg_errors	2284.570s	200000.000us	17	20	85.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	2.240s	92.848us	10	10	100.00
sec_cm_jitter_config_mubi				2	5	40.00
	clkmgr_csr_rw	1.640s	52.129us	2	5	40.00
sec_cm_idle_ctr_redun				2	5	40.00
	clkmgr_sec_cm	125.830s	10181.287us	2	5	40.00
sec_cm_meas_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.640s	52.129us	2	5	40.00
sec_cm_clk_ctrl_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.640s	52.129us	2	5	40.00
prim_count_check				2	5	40.00
	clkmgr_sec_cm	125.830s	10181.287us	2	5	40.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				1	10	10.00
	clkmgr_regwen	1.430s	27.519us	1	10	10.00
stress_all_with_rand_reset				0	10	0.00
	clkmgr_stress_all_with_rand_reset	5.680s	288.108us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				28 test runs
	clkmgr_csr_rw	69679049848123947213312174349528186021486107238378935035282137402989451689576	75	UVM_INFO @ 11063214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_aliasing	96297615405306288307325753418665160289206726203060409275549081332041440511824	75	UVM_INFO @ 24887319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	83805381674133440114196363592007077552140053837296338792164127053341827784540	75	UVM_INFO @ 7966274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	32249454846015849852783914741948718839731387048449237670215331598670085188333	112	UVM_INFO @ 35913028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	6026306653270029346712551043609840035723254327524489340697336136356045098494	80	UVM_INFO @ 5533108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	6210337053113183890865927978366518767377241691751958160639138672174305857671	87	UVM_INFO @ 75211725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	64820137973009315338381819239399186619513817634037420321272669537575021321603	80	UVM_INFO @ 3106419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	56315182298633828951881051143048223599331965704392940201570515599394888995114	80	UVM_INFO @ 17373057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	65107643736560035711366453168669128418032999151622043567319617792095930264542	75	UVM_INFO @ 11289847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	14418603834434814117455418402819700646527804856757373812346380783665736970653	97	UVM_INFO @ 14989038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	64225596533986833160347281351957844464461076311752408114517449119911848441300	75	UVM_INFO @ 4255914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	1241060844874590019736770326977920168166071781953402429750811518848152745300	91	UVM_INFO @ 20362802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	96668842111601801686288531248328853059322015347998860335568997411763617200599	90	UVM_INFO @ 14102617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	63152790085012434834657738793364475333664450598944943348482517657919509472463	80	UVM_INFO @ 12756897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	105835571023254893091517955614802226132520976336542278448432167569799175093698	83	UVM_INFO @ 3741584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	64335574401590740558929686983772405036921652241470067245374924389477457689104	80	UVM_INFO @ 3964232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	15775481960693433379953705858504979247290912888288753875470160664144364211737	80	UVM_INFO @ 5352129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	69551406207000653373250328183668402372899692293330882340485837145917904589825	75	UVM_INFO @ 18562620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	36673706515100776952999614491486360935449889167418707147966135902087451493418	80	UVM_INFO @ 3421883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	13850560708366384519715956617000906178857628573117546243949530674256564334169	80	UVM_INFO @ 1809815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	23320462865733908265517203449915697928431313585572943307741630361000059912646	75	UVM_INFO @ 26631046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	31154576336466832346598847497568393332874075674627047805873970264658659316038	98	UVM_INFO @ 36043436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	86094083473274010212623143904827517029923464542144771256579234925911822168278	75	UVM_INFO @ 5281611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	45583022639298420676487369720531482760255514899801800335187102963202895772711	80	UVM_INFO @ 4508772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	93103551050813627323626256444735187152332849633985045990080661178234014403524	88	UVM_INFO @ 9296675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	48932504749013784140821311633395885851210595566834846919180858146291989787582	80	UVM_INFO @ 5240970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	23168707208596317179990938428608383122287886783907728079350781328208331198599	85	UVM_INFO @ 6523591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	107791603216519646508640197550888408984595108809760730236794134151729723196640	99	UVM_INFO @ 90635531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				22 test runs
	clkmgr_frequency_timeout	78362046505524407702007307060168539989372048246137649357014218120030989953282	78	UVM_INFO @ 3777122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	30359763948885023233319190744088046770210064264998631666937513028460486011117	84	UVM_INFO @ 2956841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	59375076521661918074964396198773287567924877039146918678801547098683193083626	77	UVM_INFO @ 6030046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	14559365137321682227652158121317267475406483628613211681157739579739028239133	83	UVM_INFO @ 2430264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	60056344679434318815766030205311405559010739775959459760681825159272540723629	84	UVM_INFO @ 288107835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	83953608362986796929148008416531635244755974319292138882382339601743563910046	137	UVM_INFO @ 173591044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	47201606779641406262469482836794066977417979625571003911082727378243267858288	78	UVM_INFO @ 6462917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	43748793360492288210268315899085515108568916782020044214537457861867815353463	77	UVM_INFO @ 4268389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	98031191564179014560326762716919822821088058371018663769144877107281140055787	84	UVM_INFO @ 15199538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	69426420240196461306600216194545189812483490058447751153136720303815012076931	109	UVM_INFO @ 18456212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	58787706510780556270514079067145018904759101339271724335795900796654699144914	83	UVM_INFO @ 2978415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	38189629551130735954779242647583189875518961051600876205267718695562812479531	111	UVM_INFO @ 68952346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	74404587334752299196035959033578697134184367207114416180233975184650296260015	77	UVM_INFO @ 7652045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	62751647894879452965466514415380221412899692394046550058147132633376779773409	78	UVM_INFO @ 2437777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	53930829625725565870306228345301947428147224140103989027981450497573067677005	84	UVM_INFO @ 16098079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	114200704833631721604436902686657358201105803106732656273726928788376126347988	78	UVM_INFO @ 27627525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	65321220435131168934313072161647484445564018115871667665590336509435968915769	78	UVM_INFO @ 4303567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	34541816680060237373734576228366487864350790991565986961710365141518387907891	79	UVM_INFO @ 3030618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	16898687582145735677096737309334242207967403881982292637717663970299812300897	78	UVM_INFO @ 6169835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	55243140232197805716553940832882688951002415871057403383315262463228429639096	131	UVM_INFO @ 38629589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	14188625962580440983455027141714938798651894637279964562251499043036686861021	77	UVM_INFO @ 6072142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	57440563220004102823192469149167068108075221547204671050883389530127890250454	79	UVM_INFO @ 2781996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				22 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	51671703718546559761954262470555721950282156282910918583817722929735697199233	80	UVM_INFO @ 4781210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	35295223260413996315161123762244430757532021185622037921965774046109559769917	78	UVM_INFO @ 12214354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	24688976260306134139612923719909104464969390497854494369461517117821784864142	82	UVM_INFO @ 11093359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	56189235855802001189856482967324128663208122121023409834781233125247699496517	80	UVM_INFO @ 4214763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	12889073886676942503346393274528121941024228588006107430791798500173750389835	90	UVM_INFO @ 3954373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	56693983252535416500139322516411534351046096705423046321426754188638841552624	81	UVM_INFO @ 14510492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	94539361754851558061646385189662149502873902564604657123557756378095542836422	80	UVM_INFO @ 3179437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	91976677893429700360070044343053246528055236740803678022743313781997624355313	118	UVM_INFO @ 34742412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	79881038143945876853622767986130613665822263705182205654390419119996142998337	80	UVM_INFO @ 3482913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	35052854534096638130649267972359692850366055822057531959355592765125899696964	76	UVM_INFO @ 23718926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	112100037092744230531925040275801879619646702748515636029382984346754588440532	90	UVM_INFO @ 6581846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	24834834827419249467991610098170426720653825024626263505792410199795882566152	80	UVM_INFO @ 18941164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	104130824231484146220376638878265447563134711115149631303876927229616749663734	75	UVM_INFO @ 7279865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	75543233111607836675758961867467252330620625263235699426333945818846164541097	80	UVM_INFO @ 10113843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	13340997584247359141130130838587103469370130490905200790562825299420283920854	91	UVM_INFO @ 9770057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	89475733536045025178835177909858455816299950893185638663582119617290784585817	95	UVM_INFO @ 15705081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	70244638746268221417861221149220115520959411893581235325957706500366315957968	80	UVM_INFO @ 18892738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	61947423186259739736450297581990185899477197366063355486792124341001592806971	87	UVM_INFO @ 4370785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	2843319710386143714338949497527937703170749468801946371661072853922400903215	83	UVM_INFO @ 9983488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	3325714948608681200338852071844743757849495311432113506497659217991127508918	101	UVM_INFO @ 36349252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	13498877962603809796497246681901468360768749358118642666630086363065406680917	83	UVM_INFO @ 11113968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	60492538508920847492861418688263085104076352799157689417009271338687078357656	91	UVM_INFO @ 31497268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				16 test runs
	clkmgr_frequency	86517875891562344690088316619227729333762118159104809769128685039232121280037	75	UVM_INFO @ 9463590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	16917490266542779349941324148375534836479821742069728056152220059777459023770	83	UVM_INFO @ 11320628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	5760309301545359861751735592710457566058814859172991010262732149726413646686	80	UVM_INFO @ 16809985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	55076244987756666715343096097078406086814490624819262301175642392695738257185	80	UVM_INFO @ 15360112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	94967068642084098993004028742968907443939086369706907844830054905522681044971	140	UVM_INFO @ 49990598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	12267949527632872013159318763531173984290048758609210374539478576524357819204	80	UVM_INFO @ 5330185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	26223551094088041936232032454645484496996459261917318691656625088141328051658	83	UVM_INFO @ 159511754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	16057726182057007567288944005485569477060295079212329917586552494177982577378	100	UVM_INFO @ 63453383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	94446423808132824152998994984359491307028713339999856222886760763806295616352	81	UVM_INFO @ 15650780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	105664495720865237248477028273395689924456608867471984965296386399855671304282	81	UVM_INFO @ 12432576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	100874709981447056856243096771744748717256457561337927195896460372205226658449	81	UVM_INFO @ 8389557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	2916556810100569398328964802512960232484222785530834498365572633595423322222	80	UVM_INFO @ 8795255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	70589170329080191142268253920526306202113089721963632271397141231885807919812	76	UVM_INFO @ 9920040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	75607119505109626447369125188420696043851426961022216467381935365582081714996	76	UVM_INFO @ 5970499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	69794752130169792917885956712993153952965923802416628193340531486636374939353	76	UVM_INFO @ 3975911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	60997706057962292685807697641947622590165629339318925875386855629856071334596	75	UVM_INFO @ 7188891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	45534539213985034144009404664053061066423145848552510702158998060765604943465	80	UVM_INFO @ 28836146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	102688160035357600326690610940191509685756771868305550401766229743380570487625	80	UVM_INFO @ 8610189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	1064711153057369259012482769443786198205576343930081926300591627917474840307	80	UVM_INFO @ 16896428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	533347957048420849619022092511331919760765945028170880032764704811642458460	81	UVM_INFO @ 16220038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	35338541544329443678823351635036426269383451181063803904879141406568787240937	75	UVM_INFO @ 6296965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				4 test runs
	clkmgr_regwen	112995528951875606755704877529225220327506131862380752361535069112186883950698	74	UVM_INFO @ 2054798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	66773866276078081311837268719044459162476144241812269750726242426928759127321	74	UVM_INFO @ 3735086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	62448191525649892571770687863671371921720265718730348396376048745392615202333	74	UVM_INFO @ 5112584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	45790770462903471965312493130031100737515907664644075270360792853165089690752	74	UVM_INFO @ 5452674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				4 test runs
	clkmgr_regwen	35309237118845885234849036621117610069839945175199852976355192387539564059215	74	UVM_INFO @ 1975596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	82105219768215356832597085833256489738335469662685064227690657523466032435903	74	UVM_INFO @ 6629676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	108627245402866374372780416366603545708662141119965772339234051355265024941671	74	UVM_INFO @ 24219016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	5375700938399498101252773892511128909664798094648320746553029963971859113035	74	UVM_INFO @ 8527167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				3 test runs
	clkmgr_sec_cm	43390087248035408264480421114449141881249236540784131154216163654927441566629	114	UVM_INFO @ 10181287164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	114640387249324895704532540158787215993388407168063464964369915362353037958466	86	UVM_INFO @ 10016629862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	106222839874432675672620244666200083844844182145083080155340653049608964482615	87	UVM_INFO @ 10018466495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				3 test runs
	clkmgr_shadow_reg_errors	16332647628426984837429982214910967507489324596020722906269444399770669880288	80	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	15212102237556101368162025926865050450219381754187755733475622023899169576439	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	72482553208293525854790038456315874137149428030587364585408409712725578535800	80	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	clkmgr_sec_cm	33230676875635798963980244387832862744189616994502414333044137073534439119434	183	UVM_INFO @ 124304412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	64619554021300208228568320414202734028534016318322914817336182495295241442972	81	UVM_INFO @ 5161924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	41461028263939228463914506424386126608554130421490910869312594442762352196566	75	UVM_INFO @ 114242734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en				1 test run
	clkmgr_regwen	111841262542220822354337902965627121141787574283246872968646680557897980597195	74	UVM_INFO @ 5552777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---