Simulation Results

Simulation Results: csrng

12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.58 %

code
96.17 %

assert
96.94 %

func
90.62 %

block
98.49 %

line
99.50 %

branch
96.30 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.16%
V2S		98.75%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	6.000s	236.544us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	31.000s	21.235us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	31.000s	28.785us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	45.000s	567.651us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	31.000s	37.004us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	31.000s	89.800us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	31.000s	28.785us	5	5	100.00
	csrng_csr_aliasing	31.000s	37.004us	1	1	100.00

1283/1307 passed

98.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	65.000s	5665.643us	500	500	100.00
err				500	500	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
cmds				1	25	4.00
	csrng_cmds	129.000s	8773.024us	1	25	4.00
life cycle				1	25	4.00
	csrng_cmds	129.000s	8773.024us	1	25	4.00
stress_all				25	25	100.00
	csrng_stress_all	751.000s	43900.800us	25	25	100.00
intr_test				10	10	100.00
	csrng_intr_test	27.000s	25.577us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	34.000s	252.443us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	17.000s	1115.190us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	17.000s	1115.190us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	31.000s	21.235us	1	1	100.00
	csrng_csr_rw	31.000s	28.785us	5	5	100.00
	csrng_csr_aliasing	31.000s	37.004us	1	1	100.00
	csrng_same_csr_outstanding	19.000s	31.185us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	31.000s	21.235us	1	1	100.00
	csrng_csr_rw	31.000s	28.785us	5	5	100.00
	csrng_csr_aliasing	31.000s	37.004us	1	1	100.00
	csrng_same_csr_outstanding	19.000s	31.185us	5	5	100.00

V2S

1269/1285 passed

98.75 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	11.000s	255.712us	5	5	100.00
	csrng_tl_intg_err	18.000s	1151.817us	25	25	100.00
sec_cm_config_regwen				14	30	46.67
	csrng_regwen	23.000s	1.878us	9	25	36.00
	csrng_csr_rw	31.000s	28.785us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	65.000s	5665.643us	500	500	100.00
sec_cm_intersig_mubi				25	25	100.00
	csrng_stress_all	751.000s	43900.800us	25	25	100.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
	csrng_sec_cm	11.000s	255.712us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
	csrng_sec_cm	11.000s	255.712us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
	csrng_sec_cm	11.000s	255.712us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
	csrng_sec_cm	11.000s	255.712us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
	csrng_sec_cm	11.000s	255.712us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	65.000s	5665.643us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
sec_cm_constants_lc_gated				25	25	100.00
	csrng_stress_all	751.000s	43900.800us	25	25	100.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	65.000s	5665.643us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	18.000s	1151.817us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
	csrng_sec_cm	11.000s	255.712us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00
	csrng_sec_cm	11.000s	255.712us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	34.000s	96.096us	200	200	100.00
	csrng_err	31.000s	39.555us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				22 test runs
	csrng_cmds	68641373459686514861004310285582807679139557226078061488358517857866056944389	100	UVM_INFO @ 170013706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	113883408162251701733657625418558356735626885128992280757078983924733393256306	100	UVM_INFO @ 97125555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	108066080318376776637584160522271176226821489724611503157600483307214271779494	100	UVM_INFO @ 710488662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	87541541946545344406426940934116368054139353989387200674320508892479865072078	100	UVM_INFO @ 172648580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	84401972602223010650631426007821185812624537307189555034510873078023692335752	100	UVM_INFO @ 69426058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48791905565825756430753753854725830319010568102179162505445792401305508979727	100	UVM_INFO @ 1022881716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	57672321054732538957942765579192472801857253205844054874463538152032858036433	100	UVM_INFO @ 32577200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	22676747436070937139222895770216386044985744123948521596748888852815618507518	100	UVM_INFO @ 68679007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	49939475233392591555442294180469860928791089159766596895327737456301047523662	109	UVM_INFO @ 16888524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	28868636027271057599468292978603543195775545734658305162638343936069509403813	100	UVM_INFO @ 56806720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	51216002971111465824223155591576442955301946737053057324637810615577388099787	120	UVM_INFO @ 609956709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	7186096263400869770082349814129007246425722963868138554330482656432727100301	110	UVM_INFO @ 502973603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	97140901217933864589850694390339078319157943859577824196467718553308077477041	100	UVM_INFO @ 434483462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	39501895004399643786581674153509190818476450611569591022395464441158381227109	100	UVM_INFO @ 128374142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15916432715228684751855958959799851366045581012330439074568010610051219804925	100	UVM_INFO @ 97994654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	13016422813351911026159773732970315206592375794872108008759104621181901798986	100	UVM_INFO @ 56201700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	96393808282529803729984349591184469350743481155916805512128959847947141841934	110	UVM_INFO @ 144428846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	22703126020404005915341568277630876310058972004479454349591523633893115815436	100	UVM_INFO @ 355675012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	108433652439102643844943566654915463385253106642572684288112915744368039918209	100	UVM_INFO @ 193987913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	3229873466527216323981755105435045756193139045233562676187759174194330726377	100	UVM_INFO @ 69182905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	52212581963345774317025984843193427200190525492505901699405572130613206408522	100	UVM_INFO @ 17633833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	19136057194503305424209709214801382086736740377120780283051973292247663344706	100	UVM_INFO @ 65362335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				12 test runs
	csrng_regwen	71578637398315361431978858533293907347361918045624891269168359012499134380789	99	UVM_INFO @ 1877897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	113493590251713817053450974491537766946119384828057455532254725663890743999135	99	UVM_INFO @ 56857873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	62278986704525959538691544994073302179512265976283017244139840506850671154973	99	UVM_INFO @ 2836154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	22004424840551135522309366402334204040818685980940093133552917272229392843349	99	UVM_INFO @ 9540371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	31918857235196015211051845196064216114383427774814475113839586916334682823928	99	UVM_INFO @ 3583729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	69732648551647881061444932946889761218651552330018122610395155369534664055132	99	UVM_INFO @ 4896198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	83115693741766778142247285579189876546492692610141819918249325341661740777862	99	UVM_INFO @ 2516818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	35691072536649348032960004959685010910112269842144203054317715265136032736015	99	UVM_INFO @ 11922186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	23768434634001152237814562447790013148070435984087238420009483691614034694048	99	UVM_INFO @ 7354697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	112531259832197663276306404512669207761836234689012943297690467697847039236124	99	UVM_INFO @ 5670272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	35251394306975913579028487803619134551523903141957008576886016671476461766902	99	UVM_INFO @ 2530548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	97496564923383115589715198023920273665692812747840617153063664604909618248478	99	UVM_INFO @ 1573147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				8 test runs
	csrng_stress_all_with_rand_reset	12213409192144529710461138014430576616020398160925603372831426542165901169638	None
	csrng_stress_all_with_rand_reset	110236119371208469586946276551337666833408845742968074057311705663778020977852	None
	csrng_stress_all_with_rand_reset	2412102381116105032739647078080827612391938353210988782447414440301442528611	None
	csrng_stress_all_with_rand_reset	78023708982873230030335799333059307520929848437627510520029948785164891746306	None
	csrng_stress_all_with_rand_reset	87195509356219300910064937709088440471293757443232382863281342061263445400527	None
	csrng_stress_all_with_rand_reset	90471641491908989796811559084142251467770618141109862549228115182665162158897	None
	csrng_stress_all_with_rand_reset	113685024903055245264809527162522126147887140000000529103691425253743432991477	None
	csrng_stress_all_with_rand_reset	94522190970635783548834597977122771045016246620044285985592711772146912430377	None
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				4 test runs
	csrng_regwen	26874268712078290005305405821887041372512445424048534558380129911005079595571	99	UVM_INFO @ 1425714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	31051359727509865879677270797860774476920015092856497111021033093478382509635	99	UVM_INFO @ 4076532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	33021044755547238954899006347933468300681715428895365866812480769272025752814	99	UVM_INFO @ 1434417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	55100322709245852781131801591221550587971764762548356846474181493349272072002	99	UVM_INFO @ 2731378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				2 test runs
	csrng_cmds	62447728419689257757625603994179998616293555235183821039490904906952002294027	103	UVM_INFO @ 333722204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	94932071348847758625616068998757451703490089798560407014852499929871657550411	103	UVM_INFO @ 310629987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				1 test run
	csrng_stress_all_with_rand_reset	76987864928745944913788774726125921893211693458486826387155621055350303442503	120	UVM_INFO @ 132919560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:348) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (* [] vs [*])				1 test run
	csrng_stress_all_with_rand_reset	19142904144813721200446509739549473070387177860215913087836942797074873757412	104	UVM_INFO @ 128147515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---