Simulation Results

Simulation Results: edn/edn0

12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
84.25 %

code
95.26 %

assert
98.89 %

func
58.60 %

block
96.95 %

line
98.68 %

branch
93.23 %

toggle
89.13 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		98.68%
V2S		100.00%
V3		83.33%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	edn_smoke	2.000s	22.766us	10	10	100.00
csr_hw_reset				1	1	100.00
	edn_csr_hw_reset	2.000s	28.655us	1	1	100.00
csr_rw				5	5	100.00
	edn_csr_rw	2.000s	30.439us	5	5	100.00
csr_bit_bash				1	1	100.00
	edn_csr_bit_bash	3.000s	170.610us	1	1	100.00
csr_aliasing				1	1	100.00
	edn_csr_aliasing	3.000s	47.692us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	edn_csr_mem_rw_with_rand_reset	2.000s	42.628us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	edn_csr_rw	2.000s	30.439us	5	5	100.00
	edn_csr_aliasing	3.000s	47.692us	1	1	100.00

599/607 passed

98.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				100	100	100.00
	edn_genbits	7.000s	42.696us	100	100	100.00
csrng_commands				100	100	100.00
	edn_genbits	7.000s	42.696us	100	100	100.00
genbits				100	100	100.00
	edn_genbits	7.000s	42.696us	100	100	100.00
interrupts				20	20	100.00
	edn_intr	2.000s	29.608us	20	20	100.00
alerts				200	200	100.00
	edn_alert	7.000s	28.742us	200	200	100.00
errs				100	100	100.00
	edn_err	6.000s	32.113us	100	100	100.00
disable				92	100	92.00
	edn_disable	2.000s	12.660us	50	50	100.00
	edn_disable_auto_req_mode	10.000s	500.000us	42	50	84.00
stress_all				30	30	100.00
	edn_stress_all	7.000s	1027.457us	30	30	100.00
intr_test				10	10	100.00
	edn_intr_test	2.000s	29.086us	10	10	100.00
alert_test				10	10	100.00
	edn_alert_test	2.000s	21.633us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	edn_tl_errors	5.000s	275.420us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	edn_tl_errors	5.000s	275.420us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	edn_csr_hw_reset	2.000s	28.655us	1	1	100.00
	edn_csr_rw	2.000s	30.439us	5	5	100.00
	edn_csr_aliasing	3.000s	47.692us	1	1	100.00
	edn_same_csr_outstanding	2.000s	47.290us	5	5	100.00
tl_d_partial_access				12	12	100.00
	edn_csr_hw_reset	2.000s	28.655us	1	1	100.00
	edn_csr_rw	2.000s	30.439us	5	5	100.00
	edn_csr_aliasing	3.000s	47.692us	1	1	100.00
	edn_same_csr_outstanding	2.000s	47.290us	5	5	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	edn_sec_cm	12.000s	1755.433us	5	5	100.00
	edn_tl_intg_err	8.000s	893.600us	25	25	100.00
sec_cm_config_regwen				5	5	100.00
	edn_regwen	2.000s	15.576us	5	5	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	7.000s	28.742us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	12.000s	1755.433us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	12.000s	1755.433us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	12.000s	1755.433us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	12.000s	1755.433us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	7.000s	28.742us	200	200	100.00
	edn_sec_cm	12.000s	1755.433us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	7.000s	28.742us	200	200	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	edn_tl_intg_err	8.000s	893.600us	25	25	100.00

25/30 passed

83.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				25	30	83.33
	edn_stress_all_with_rand_reset	100.000s	21832.666us	25	30	83.33

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				8 test runs
	edn_disable_auto_req_mode	111864053067241849570980517992042157422665904577803476345504997253236780342711	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	104435262631421225025094275469083657380002079933142779322480871599150020911912	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	105844432555090494915270668277497085278316634445959758960798301261996121656328	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	14299265562493901676033850308411132476850555963671971752479642859261955063560	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	96205469914727135126485137906267145515746288411910793039458778672311183389623	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	102286550916457711372124036180272629690431973475999413163153400558738705306199	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	34300653464741748151747290450407934116650241871510483337493093040965724442344	103	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	1372513955925044356662214072851708531587870479280190786264776276581704891401	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				4 test runs
	edn_stress_all_with_rand_reset	85540171938807366443684139799656794964797408094486391970384905256717296173790	156	UVM_INFO @ 113996819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	22321556325100696907756919266576022920314347128090592395251893932667745545301	218	UVM_INFO @ 2210268226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	44388405906365647722885213855428941304441215502993415328212962934883767808337	162	UVM_INFO @ 1240176318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	77241669825917549560046974661727395367788877135306938381967228900481262829656	194	UVM_INFO @ 1092283731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1200) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	edn_stress_all_with_rand_reset	98264311662163572833777236773465850235801134095176341282059576377793558896293	150	UVM_INFO @ 819652624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---