Simulation Results: edn/edn1

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.60 %
  • code
  • 95.86 %
  • assert
  • 98.70 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.62 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
98.52%
V2S
100.00%
V3
86.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.190s 20.793us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.110s 17.957us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.250s 17.749us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.860s 315.888us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.070s 54.406us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.890s 98.680us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.250s 17.749us 5 5 100.00
edn_csr_aliasing 1.070s 54.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 7.620s 1306.946us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 7.620s 1306.946us 100 100 100.00
genbits 100 100 100.00
edn_genbits 7.620s 1306.946us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.430s 21.376us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.580s 36.475us 200 200 100.00
errs 100 100 100.00
edn_err 1.490s 28.910us 100 100 100.00
disable 91 100 91.00
edn_disable 1.200s 13.541us 50 50 100.00
edn_disable_auto_req_mode 8.160s 500.000us 41 50 82.00
stress_all 30 30 100.00
edn_stress_all 7.020s 442.638us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.170s 28.392us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.310s 19.250us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.670s 442.755us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.670s 442.755us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.110s 17.957us 1 1 100.00
edn_csr_rw 1.250s 17.749us 5 5 100.00
edn_csr_aliasing 1.070s 54.406us 1 1 100.00
edn_same_csr_outstanding 1.460s 58.006us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.110s 17.957us 1 1 100.00
edn_csr_rw 1.250s 17.749us 5 5 100.00
edn_csr_aliasing 1.070s 54.406us 1 1 100.00
edn_same_csr_outstanding 1.460s 58.006us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.110s 1100.444us 5 5 100.00
edn_tl_intg_err 2.880s 93.230us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.180s 27.684us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.580s 36.475us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.110s 1100.444us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.110s 1100.444us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.110s 1100.444us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.110s 1100.444us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.580s 36.475us 200 200 100.00
edn_sec_cm 4.110s 1100.444us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.580s 36.475us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.880s 93.230us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 30 86.67
edn_stress_all_with_rand_reset 122.480s 10270.387us 26 30 86.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 8 test runs
edn_disable_auto_req_mode 103788331223776215222072656571301283997783480979645266872128121744871194583680 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 102630186991844664303756338079764450652770535346556909508667152263314777040869 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66497007837683185750124441364055649758400883294459617114298017624443870901639 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 38897192962217655972328118562013397999131370991001421862490405029859174513737 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 88265142941737607993044948667315294077483007806321549528510586823893626421751 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 35418149909051796669472975485347672927288660642052439735506133541639527611133 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 19080205497616229880607554789454525023288941393165084081745494046875545675947 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 111255435708193218399109151823293522998309854723290790205578477804615611081757 90
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 55863627173092530398965571793748265784357042325150953243249146742501744753081 234
UVM_INFO @ 1228902935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 75896750982241635171214612705513658151161813016763375902441005688644234576049 274
UVM_INFO @ 2679835776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 24463660849672089138111605316557854489428149592106367267606159586270365229458 242
UVM_INFO @ 2570101606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 75485843426953708102448737519082353921131568627383742751853233016386336279370 321
UVM_INFO @ 16174281036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 85530447882965439511370058518692754991557699913691051967312162700982485138382 88
UVM_INFO @ 140713477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---