Simulation Results: hmac

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.11 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 14.000s 6040.925us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 67.042us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 33.443us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.000s 3829.278us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.000s 182.332us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 518.000s 96155.824us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 33.443us 5 5 100.00
hmac_csr_aliasing 4.000s 182.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 77.000s 7517.289us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 124.000s 3164.729us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 317.000s 37812.799us 30 30 100.00
hmac_test_sha384_vectors 633.000s 20104.687us 75 75 100.00
hmac_test_sha512_vectors 638.000s 74294.886us 75 75 100.00
hmac_test_hmac256_vectors 32.000s 672.998us 50 50 100.00
hmac_test_hmac384_vectors 38.000s 2088.388us 60 60 100.00
hmac_test_hmac512_vectors 30.000s 1400.170us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 39.000s 2946.509us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 364.000s 72290.080us 10 10 100.00
error 10 10 100.00
hmac_error 142.000s 46617.063us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 153.000s 56030.743us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 14.000s 6040.925us 10 10 100.00
hmac_long_msg 77.000s 7517.289us 10 10 100.00
hmac_back_pressure 124.000s 3164.729us 25 25 100.00
hmac_datapath_stress 364.000s 72290.080us 10 10 100.00
hmac_burst_wr 39.000s 2946.509us 50 50 100.00
hmac_stress_all 1228.000s 118369.667us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 14.000s 6040.925us 10 10 100.00
hmac_long_msg 77.000s 7517.289us 10 10 100.00
hmac_back_pressure 124.000s 3164.729us 25 25 100.00
hmac_datapath_stress 364.000s 72290.080us 10 10 100.00
hmac_wipe_secret 153.000s 56030.743us 10 10 100.00
hmac_test_sha256_vectors 317.000s 37812.799us 30 30 100.00
hmac_test_sha384_vectors 633.000s 20104.687us 75 75 100.00
hmac_test_sha512_vectors 638.000s 74294.886us 75 75 100.00
hmac_test_hmac256_vectors 32.000s 672.998us 50 50 100.00
hmac_test_hmac384_vectors 38.000s 2088.388us 60 60 100.00
hmac_test_hmac512_vectors 30.000s 1400.170us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 14.000s 6040.925us 10 10 100.00
hmac_long_msg 77.000s 7517.289us 10 10 100.00
hmac_back_pressure 124.000s 3164.729us 25 25 100.00
hmac_datapath_stress 364.000s 72290.080us 10 10 100.00
hmac_burst_wr 39.000s 2946.509us 50 50 100.00
hmac_error 142.000s 46617.063us 10 10 100.00
hmac_wipe_secret 153.000s 56030.743us 10 10 100.00
hmac_test_sha256_vectors 317.000s 37812.799us 30 30 100.00
hmac_test_sha384_vectors 633.000s 20104.687us 75 75 100.00
hmac_test_sha512_vectors 638.000s 74294.886us 75 75 100.00
hmac_test_hmac256_vectors 32.000s 672.998us 50 50 100.00
hmac_test_hmac384_vectors 38.000s 2088.388us 60 60 100.00
hmac_test_hmac512_vectors 30.000s 1400.170us 75 75 100.00
hmac_stress_all 1228.000s 118369.667us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1228.000s 118369.667us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 7.000s 21.693us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 18.301us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 5.000s 758.812us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 5.000s 758.812us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 67.042us 1 1 100.00
hmac_csr_rw 2.000s 33.443us 5 5 100.00
hmac_csr_aliasing 4.000s 182.332us 1 1 100.00
hmac_same_csr_outstanding 4.000s 140.194us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 67.042us 1 1 100.00
hmac_csr_rw 2.000s 33.443us 5 5 100.00
hmac_csr_aliasing 4.000s 182.332us 1 1 100.00
hmac_same_csr_outstanding 4.000s 140.194us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 36.214us 5 5 100.00
hmac_tl_intg_err 5.000s 512.662us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.000s 512.662us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 14.000s 6040.925us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.000s 707.061us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 334.000s 28447.439us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 31.765us 1 1 100.00