Simulation Results: lc_ctrl/volatile_unlock_disabled

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.23 %
  • code
  • 93.18 %
  • assert
  • 96.69 %
  • func
  • 89.81 %
  • block
  • 96.70 %
  • line
  • 97.39 %
  • branch
  • 91.61 %
  • toggle
  • 88.48 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.000s 571.590us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 17.000s 20.506us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 160.333us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 22.000s 125.337us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 24.000s 46.048us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 7.000s 111.923us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 160.333us 5 5 100.00
lc_ctrl_csr_aliasing 24.000s 46.048us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 5.000s 381.284us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 9.000s 992.288us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 24.000s 12.279us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 117.401us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 12.000s 1588.258us 20 20 100.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_ctrl_prog_failure 4.000s 117.401us 20 20 100.00
lc_ctrl_errors 12.000s 1588.258us 20 20 100.00
lc_ctrl_security_escalation 10.000s 471.770us 20 20 100.00
lc_ctrl_jtag_state_failure 48.000s 36110.688us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.000s 1928.566us 18 20 90.00
lc_ctrl_jtag_errors 78.000s 58038.718us 20 20 100.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 10.000s 976.769us 20 20 100.00
lc_ctrl_jtag_state_post_trans 19.000s 1975.960us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.000s 1928.566us 18 20 90.00
lc_ctrl_jtag_errors 78.000s 58038.718us 20 20 100.00
lc_ctrl_jtag_access 19.000s 862.630us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 24.000s 2719.583us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 533.858us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.000s 523.682us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 23.000s 2121.438us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 6082.498us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 110.303us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 576.876us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 393.218us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 21.000s 4824.342us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 11.940us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 208.000s 11679.524us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 24.000s 31.707us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 529.369us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 529.369us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 17.000s 20.506us 1 1 100.00
lc_ctrl_csr_rw 2.000s 160.333us 5 5 100.00
lc_ctrl_csr_aliasing 24.000s 46.048us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 23.881us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 17.000s 20.506us 1 1 100.00
lc_ctrl_csr_rw 2.000s 160.333us 5 5 100.00
lc_ctrl_csr_aliasing 24.000s 46.048us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 23.881us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 884.900us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 675.251us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 675.251us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 9.000s 992.288us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_ctrl_sec_cm 4.000s 884.900us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_ctrl_sec_cm 4.000s 884.900us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_ctrl_sec_cm 4.000s 884.900us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_ctrl_sec_cm 4.000s 884.900us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_ctrl_sec_cm 4.000s 884.900us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_ctrl_sec_cm 4.000s 884.900us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_ctrl_sec_cm 4.000s 884.900us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 10.000s 1321.112us 20 20 100.00
lc_ctrl_sec_cm 4.000s 884.900us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 10.000s 471.770us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 5.000s 381.284us 20 20 100.00
lc_ctrl_jtag_state_post_trans 19.000s 1975.960us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 15.000s 734.937us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 15.000s 734.937us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.000s 646.015us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 582.062us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 582.062us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 70.000s 4459.471us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 1515229398706258499000096572260586629206384358908162569335515805687203536803 683
UVM_INFO @ 1508110710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13150310467880331930313561277944591732913350244631626679166588931523129178996 6644
UVM_INFO @ 4459471454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19385180451265761485376121783127383771730596708799829343487244099364286747585 183
UVM_INFO @ 115817376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14023119240416347058624169552217033733574598776593469164884895612636399740938 2478
UVM_INFO @ 3576671572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9023637487519398677651349093733297781014791660380631434457061677281140122966 167
UVM_INFO @ 2915031876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_prog_failure 23319178956640954005024753216916416241689635226221335097007453842339681598558 179
UVM_INFO @ 373738180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 93811251050955071648577480387334860126853180517010596823156457726863566291509 177
UVM_INFO @ 35979638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 65986037011079511329689777223771528268744723571141950830269975240301138224015 1341
UVM_INFO @ 3283671859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---