Simulation Results: lc_ctrl/volatile_unlock_enabled

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.78 %
  • code
  • 94.19 %
  • assert
  • 96.69 %
  • func
  • 90.45 %
  • block
  • 97.20 %
  • line
  • 97.72 %
  • branch
  • 92.91 %
  • toggle
  • 88.51 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.06%
V2S
99.33%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.000s 111.183us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 17.635us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 15.187us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 89.627us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 19.618us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 142.127us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 15.187us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 19.618us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 71.889us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 7.000s 214.853us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 40.250us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 85.406us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 14.000s 665.026us 20 20 100.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_ctrl_prog_failure 4.000s 85.406us 20 20 100.00
lc_ctrl_errors 14.000s 665.026us 20 20 100.00
lc_ctrl_security_escalation 10.000s 1319.773us 20 20 100.00
lc_ctrl_jtag_state_failure 57.000s 12817.071us 19 20 95.00
lc_ctrl_jtag_prog_failure 10.000s 2379.383us 19 20 95.00
lc_ctrl_jtag_errors 72.000s 46070.922us 20 20 100.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 6.000s 311.799us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 5306.985us 19 20 95.00
lc_ctrl_jtag_prog_failure 10.000s 2379.383us 19 20 95.00
lc_ctrl_jtag_errors 72.000s 46070.922us 20 20 100.00
lc_ctrl_jtag_access 21.000s 1306.134us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 23.000s 5248.623us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 147.373us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 547.599us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 31.000s 2249.470us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 12.000s 939.365us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 96.835us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.000s 800.375us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 195.776us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 9.000s 1249.631us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 17.060us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 148.000s 15555.122us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 3.000s 73.596us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 144.477us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 144.477us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.000s 17.635us 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.187us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 19.618us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 185.116us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.000s 17.635us 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.187us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 19.618us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 185.116us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 870.611us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 1375.280us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 1375.280us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 7.000s 214.853us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_ctrl_sec_cm 4.000s 870.611us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_ctrl_sec_cm 4.000s 870.611us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_ctrl_sec_cm 4.000s 870.611us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_ctrl_sec_cm 4.000s 870.611us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_ctrl_sec_cm 4.000s 870.611us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_ctrl_sec_cm 4.000s 870.611us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_ctrl_sec_cm 4.000s 870.611us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 9.000s 1571.015us 20 20 100.00
lc_ctrl_sec_cm 4.000s 870.611us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 10.000s 1319.773us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 4.000s 71.889us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 5306.985us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 1903.942us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 1903.942us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 9.000s 401.414us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.000s 646.460us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.000s 646.460us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 61.000s 15567.568us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 32874956314766632699193328637011033462921463518053737297183223856097911244313 166
UVM_INFO @ 1083881168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87032529494152037576356637156332435556230154116802686118399574835032416297402 3300
UVM_INFO @ 2158552457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20040354634480830874350160464691413121999569061595302728534259097323431183798 2852
UVM_INFO @ 5901720461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68728134798678527912653792893806740236243312914348895520038953904445649609344 2479
UVM_INFO @ 5448853724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99273244664113164096240154205383555114195006424083314594906517216195576296959 192
UVM_INFO @ 281004253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47505376352213924895836959323661390491068205174433326631673667975443338369777 183
UVM_INFO @ 2201757248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 37932845571626116462495297462702398095298319789174494759122227176553337275997 177
UVM_INFO @ 27478615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 89996184974061068048624469129237277422347654659780184376877066490414508365079 177
UVM_INFO @ 351031842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 69376767720678846976155708647832637472085590391941820906740916668945967072200 3041
UVM_INFO @ 1399612692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 4359176039550154999163426446844262097233256407841850067294634548482403166578 178
UVM_INFO @ 93303431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---