Simulation Results

Simulation Results: otbn

12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
97.88 %

code
95.64 %

assert
98.01 %

func
100.00 %

block
99.46 %

line
99.60 %

branch
93.14 %

toggle
89.81 %

FSM
100.00 %

Validation stages

V1		99.14%
V2		98.77%
V2S		96.66%
V3		20.00%
unmapped		100.00%

115/116 passed

99.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	9.000s	70.592us	1	1	100.00
single_binary				99	100	99.00
	otbn_single	37.000s	125.406us	99	100	99.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	10.000s	24.153us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	8.000s	43.012us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	10.000s	56.879us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	8.000s	35.808us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	13.000s	59.667us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	8.000s	43.012us	5	5	100.00
	otbn_csr_aliasing	8.000s	35.808us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	75.000s	3236.982us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	24.000s	5553.656us	1	1	100.00

161/163 passed

98.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	44.000s	113.108us	10	10	100.00
multi_error				1	1	100.00
	otbn_multi_err	55.000s	196.961us	1	1	100.00
back_to_back				10	10	100.00
	otbn_multi	95.000s	346.725us	10	10	100.00
stress_all				10	10	100.00
	otbn_stress_all	678.000s	1938.703us	10	10	100.00
lc_escalation				59	60	98.33
	otbn_escalate	346.000s	1337.417us	59	60	98.33
zero_state_err_urnd				4	5	80.00
	otbn_zero_state_err_urnd	8.000s	25.574us	4	5	80.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	12.000s	128.689us	10	10	100.00
alert_test				10	10	100.00
	otbn_alert_test	9.000s	65.747us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	7.000s	52.570us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	9.000s	258.067us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	9.000s	258.067us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	10.000s	24.153us	1	1	100.00
	otbn_csr_rw	8.000s	43.012us	5	5	100.00
	otbn_csr_aliasing	8.000s	35.808us	1	1	100.00
	otbn_same_csr_outstanding	6.000s	30.140us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	10.000s	24.153us	1	1	100.00
	otbn_csr_rw	8.000s	43.012us	5	5	100.00
	otbn_csr_aliasing	8.000s	35.808us	1	1	100.00
	otbn_same_csr_outstanding	6.000s	30.140us	5	5	100.00

V2S

318/329 passed

96.66 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				25	25	100.00
	otbn_imem_err	11.000s	65.318us	10	10	100.00
	otbn_dmem_err	38.000s	155.715us	15	15	100.00
internal_integrity				15	17	88.24
	otbn_alu_bignum_mod_err	13.000s	71.742us	4	5	80.00
	otbn_controller_ispr_rdata_err	16.000s	115.376us	5	5	100.00
	otbn_mac_bignum_acc_err	22.000s	147.705us	4	5	80.00
	otbn_urnd_err	12.000s	49.466us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	9.000s	26.662us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	7.000s	39.597us	2	2	100.00
otbn_non_sec_partial_wipe				9	10	90.00
	otbn_partial_wipe	7.000s	22.355us	9	10	90.00
tl_intg_err				30	30	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
	otbn_tl_intg_err	61.000s	363.291us	25	25	100.00
passthru_mem_tl_intg_err				3	5	60.00
	otbn_passthru_mem_tl_intg_err	53.000s	192.167us	3	5	60.00
prim_fsm_check				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
prim_count_check				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	9.000s	70.592us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	38.000s	155.715us	15	15	100.00
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	11.000s	65.318us	10	10	100.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	61.000s	363.291us	25	25	100.00
sec_cm_controller_fsm_global_esc				59	60	98.33
	otbn_escalate	346.000s	1337.417us	59	60	98.33
sec_cm_controller_fsm_local_esc				39	40	97.50
	otbn_imem_err	11.000s	65.318us	10	10	100.00
	otbn_dmem_err	38.000s	155.715us	15	15	100.00
	otbn_zero_state_err_urnd	8.000s	25.574us	4	5	80.00
	otbn_illegal_mem_acc	9.000s	26.662us	5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_controller_fsm_sparse				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_scramble_key_sideload				99	100	99.00
	otbn_single	37.000s	125.406us	99	100	99.00
sec_cm_scramble_ctrl_fsm_local_esc				39	40	97.50
	otbn_imem_err	11.000s	65.318us	10	10	100.00
	otbn_dmem_err	38.000s	155.715us	15	15	100.00
	otbn_zero_state_err_urnd	8.000s	25.574us	4	5	80.00
	otbn_illegal_mem_acc	9.000s	26.662us	5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_scramble_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_global_esc				59	60	98.33
	otbn_escalate	346.000s	1337.417us	59	60	98.33
sec_cm_start_stop_ctrl_fsm_local_esc				39	40	97.50
	otbn_imem_err	11.000s	65.318us	10	10	100.00
	otbn_dmem_err	38.000s	155.715us	15	15	100.00
	otbn_zero_state_err_urnd	8.000s	25.574us	4	5	80.00
	otbn_illegal_mem_acc	9.000s	26.662us	5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_data_reg_sw_sca				99	100	99.00
	otbn_single	37.000s	125.406us	99	100	99.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	10.000s	30.212us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	9.000s	24.670us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	691.000s	3131.640us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	691.000s	3131.640us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	10.000s	36.956us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_stack_wr_ptr_ctr_redun				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_rf_bignum_data_reg_sw_integrity				9	10	90.00
	otbn_rf_bignum_intg_err	12.000s	68.956us	9	10	90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_loop_stack_ctr_redun				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00
sec_cm_loop_stack_addr_integrity				3	5	60.00
	otbn_stack_addr_integ_chk	8.000s	117.652us	3	5	60.00
sec_cm_call_stack_addr_integrity				3	5	60.00
	otbn_stack_addr_integ_chk	8.000s	117.652us	3	5	60.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	137.000s	502.179us	7	7	100.00
sec_cm_data_mem_sec_wipe				99	100	99.00
	otbn_single	37.000s	125.406us	99	100	99.00
sec_cm_instruction_mem_sec_wipe				99	100	99.00
	otbn_single	37.000s	125.406us	99	100	99.00
sec_cm_data_reg_sw_sec_wipe				99	100	99.00
	otbn_single	37.000s	125.406us	99	100	99.00
sec_cm_write_mem_integrity				10	10	100.00
	otbn_multi	95.000s	346.725us	10	10	100.00
sec_cm_ctrl_flow_count				99	100	99.00
	otbn_single	37.000s	125.406us	99	100	99.00
sec_cm_ctrl_flow_sca				99	100	99.00
	otbn_single	37.000s	125.406us	99	100	99.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	15.000s	77.354us	5	5	100.00
sec_cm_key_sideload				99	100	99.00
	otbn_single	37.000s	125.406us	99	100	99.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	otbn_sec_cm	498.000s	2506.400us	5	5	100.00

2/10 passed

20.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	10	20.00
	otbn_stress_all_with_rand_reset	424.000s	4317.227us	2	10	20.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	9.000s	69.760us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				5 test runs
	otbn_stress_all_with_rand_reset	25644833848797621927752366404259317358193009081348915168123986881642933734348	155	UVM_INFO @ 188075458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	37303835261032623042155007216907545344195495585575179117867745222685785941530	267	UVM_INFO @ 1133323565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	8366287315716125175282307763273991321638661846884401776761600940612627543662	301	UVM_INFO @ 859913998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	56121487784484074582177850570409229453437032189337631529235303507568612688294	593	UVM_INFO @ 4317226723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	96203893265846561535698174089385065596957250962136466829533357418317734382118	239	UVM_INFO @ 444416167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error				4 test runs
	otbn_alu_bignum_mod_err	17291558785376563023307499307910444051893599989726766023155432044842809020532	121	UVM_INFO @ 244104690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_mac_bignum_acc_err	90188766609126221513257458445662058441350479198683730899974572239000742972418	122	UVM_INFO @ 75141111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_bignum_intg_err	88776412807504217234511244017194452284599214301857742803577243726203575133661	111	UVM_INFO @ 178376703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	63175072073311968171165291524716879076548391928172533862287679593454457965638	110	UVM_INFO @ 112406682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed				3 test runs
	otbn_zero_state_err_urnd	98395653179058879236886285277610473074255094070474165442329796289760566119123	109	UVM_ERROR @ 23210210 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 23210210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stack_addr_integ_chk	112960050785952678310050229488595416645109375467324938510528819005155687577311	113	UVM_ERROR @ 20484444 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 20484444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stack_addr_integ_chk	57273169823593610731790189257682217974588985052160441726394505019193661207699	115	UVM_ERROR @ 19422279 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 19422279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	otbn_stress_all_with_rand_reset	20328899059966616088569237733972345697038594958325768587340887284977067511534	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
	otbn_stress_all_with_rand_reset	56961601412637439604482019984455357310996074789892956352193578072832041712850	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.				2 test runs
	otbn_passthru_mem_tl_intg_err	111054996189612210188378093880687162154113680084674130750814349689695528313828	91	UVM_INFO @ 29056178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_single	2189182402675092868428190588295727449151479450515052967674508230374467665989	107	UVM_INFO @ 35321008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [] vs [*]) value for register otbn_reg_block.status				1 test run
	otbn_partial_wipe	20621044768413325287436415663299217095508738455125829729758250943707751638355	117	UVM_INFO @ 8471409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.				1 test run
	otbn_passthru_mem_tl_intg_err	93983049802548838678225814439710310822017173664898324878963799325764970115111	86	UVM_INFO @ 4172830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)				1 test run
	otbn_stress_all_with_rand_reset	30626256387645513910923874622649289498356798958144116057191072099925408013185	146	UVM_INFO @ 13598785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---