Simulation Results

Simulation Results: rom_ctrl/32kb

12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
96.99 %

code
94.00 %

assert
97.67 %

func
99.29 %

block
96.76 %

line
97.24 %

branch
94.09 %

toggle
84.66 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		97.18%
V2S		98.31%
V3		85.00%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	5.000s	135.118us	2	2	100.00
csr_hw_reset				1	1	100.00
	rom_ctrl_csr_hw_reset	4.000s	546.614us	1	1	100.00
csr_rw				5	5	100.00
	rom_ctrl_csr_rw	4.000s	128.547us	5	5	100.00
csr_bit_bash				1	1	100.00
	rom_ctrl_csr_bit_bash	4.000s	171.544us	1	1	100.00
csr_aliasing				1	1	100.00
	rom_ctrl_csr_aliasing	4.000s	558.515us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	6.000s	192.541us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rom_ctrl_csr_rw	4.000s	128.547us	5	5	100.00
	rom_ctrl_csr_aliasing	4.000s	558.515us	1	1	100.00
mem_walk				1	1	100.00
	rom_ctrl_mem_walk	4.000s	169.044us	1	1	100.00
mem_partial_access				1	1	100.00
	rom_ctrl_mem_partial_access	4.000s	558.382us	1	1	100.00

69/71 passed

97.18 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				0	2	0.00
	rom_ctrl_max_throughput_chk	3.000s	347.711us	0	2	0.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	19.000s	4194.927us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	6.000s	1082.079us	2	2	100.00
alert_test				10	10	100.00
	rom_ctrl_alert_test	5.000s	370.616us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rom_ctrl_tl_errors	9.000s	201.048us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rom_ctrl_tl_errors	9.000s	201.048us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rom_ctrl_csr_hw_reset	4.000s	546.614us	1	1	100.00
	rom_ctrl_csr_rw	4.000s	128.547us	5	5	100.00
	rom_ctrl_csr_aliasing	4.000s	558.515us	1	1	100.00
	rom_ctrl_same_csr_outstanding	5.000s	2093.477us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rom_ctrl_csr_hw_reset	4.000s	546.614us	1	1	100.00
	rom_ctrl_csr_rw	4.000s	128.547us	5	5	100.00
	rom_ctrl_csr_aliasing	4.000s	558.515us	1	1	100.00
	rom_ctrl_same_csr_outstanding	5.000s	2093.477us	5	5	100.00

V2S

58/59 passed

98.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				19	20	95.00
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
passthru_mem_tl_intg_err				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	16.000s	831.310us	5	5	100.00
tl_intg_err				30	30	100.00
	rom_ctrl_sec_cm	126.000s	921.074us	5	5	100.00
	rom_ctrl_tl_intg_err	34.000s	799.641us	25	25	100.00
prim_fsm_check				5	5	100.00
	rom_ctrl_sec_cm	126.000s	921.074us	5	5	100.00
prim_count_check				5	5	100.00
	rom_ctrl_sec_cm	126.000s	921.074us	5	5	100.00
sec_cm_checker_ctr_consistency				19	20	95.00
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
sec_cm_checker_ctrl_flow_consistency				19	20	95.00
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
sec_cm_checker_fsm_local_esc				19	20	95.00
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
sec_cm_compare_ctrl_flow_consistency				19	20	95.00
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
sec_cm_compare_ctr_consistency				19	20	95.00
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
sec_cm_compare_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	126.000s	921.074us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	rom_ctrl_sec_cm	126.000s	921.074us	5	5	100.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	5.000s	135.118us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	5.000s	135.118us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	5.000s	135.118us	2	2	100.00
sec_cm_bus_integrity				25	25	100.00
	rom_ctrl_tl_intg_err	34.000s	799.641us	25	25	100.00
sec_cm_bus_local_esc				21	22	95.45
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
	rom_ctrl_kmac_err_chk	6.000s	1082.079us	2	2	100.00
sec_cm_mux_mubi				19	20	95.00
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
sec_cm_mux_consistency				19	20	95.00
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
sec_cm_ctrl_redun				19	20	95.00
	rom_ctrl_corrupt_sig_fatal_chk	75.000s	11272.732us	19	20	95.00
sec_cm_ctrl_mem_integrity				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	16.000s	831.310us	5	5	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	126.000s	921.074us	5	5	100.00

17/20 passed

85.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				17	20	85.00
	rom_ctrl_stress_all_with_rand_reset	116.000s	10766.658us	17	20	85.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:*				3 test runs
	rom_ctrl_stress_all_with_rand_reset	78969040079650701350529757224150691811409408145959967927230733316788139227612	91	UVM_INFO @ 296881544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	63472272309053724018021876205138893390901098780943368292976508580932378881059	92	UVM_INFO @ 1195857065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	31434231438475974887108445814529729802164606110177085550217525844169341814349	89	UVM_INFO @ 696150771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [] vs [*])				2 test runs
	rom_ctrl_max_throughput_chk	65459590214320657438661452871160325498207090149955268537184603467933475376560	88	UVM_INFO @ 347711276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_max_throughput_chk	77643132553854988947424832917624547244513377795588726661160399738509660997229	88	UVM_INFO @ 491482179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)				1 test run
	rom_ctrl_corrupt_sig_fatal_chk	30352494512648293457136987052713751606908679239553943314814983202712604148137	101	UVM_INFO @ 2458024556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---