Simulation Results: rom_ctrl/64kb

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.99 %
  • code
  • 94.01 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.77%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 9.000s 310.028us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 1076.630us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 6.000s 217.129us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.000s 534.241us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 296.855us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 9.000s 629.606us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 6.000s 217.129us 5 5 100.00
rom_ctrl_csr_aliasing 6.000s 296.855us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.000s 212.169us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.000s 297.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 7.000s 505.593us 0 2 0.00
stress_all 19 20 95.00
rom_ctrl_stress_all 32.000s 1113.709us 19 20 95.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 11.000s 1058.307us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 9.000s 4304.557us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 10.000s 301.199us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 10.000s 301.199us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.000s 1076.630us 1 1 100.00
rom_ctrl_csr_rw 6.000s 217.129us 5 5 100.00
rom_ctrl_csr_aliasing 6.000s 296.855us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 306.722us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.000s 1076.630us 1 1 100.00
rom_ctrl_csr_rw 6.000s 217.129us 5 5 100.00
rom_ctrl_csr_aliasing 6.000s 296.855us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 306.722us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.000s 12169.373us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 230.000s 651.394us 5 5 100.00
rom_ctrl_tl_intg_err 71.000s 1521.583us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 230.000s 651.394us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 230.000s 651.394us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 230.000s 651.394us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 230.000s 651.394us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 9.000s 310.028us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 9.000s 310.028us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 9.000s 310.028us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 71.000s 1521.583us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
rom_ctrl_kmac_err_chk 11.000s 1058.307us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.000s 17335.527us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.000s 12169.373us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 230.000s 651.394us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
rom_ctrl_stress_all_with_rand_reset 98.000s 8610.822us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 3 test runs
rom_ctrl_stress_all_with_rand_reset 42976796631084277210968684624233611349059735984939107669261447807779702630811 91
UVM_INFO @ 179488685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all 31270330415640857716577506372752844209842404861162217053851774705689822940637 87
UVM_INFO @ 667377390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 5406471479540077109103504831275806936516343170334959306514875185367236646962 91
UVM_INFO @ 323487761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 1313807237667170370171730079422511902457783102567613807824796930929011660774 88
UVM_INFO @ 505592593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 88304926992413952904926771955164710654726305572328519130432137026187568654499 88
UVM_INFO @ 1071360878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---