Simulation Results: rstmgr_cnsty_chk

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 95.05 %
  • assert
  • 100.00 %
  • line
  • 98.41 %
  • branch
  • 98.31 %
  • cond
  • 86.21 %
  • toggle
  • 100.00 %
  • FSM
  • 92.31 %
Validation stages
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
rstmgr_cnsty_chk_test 4.240s 10492.009us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) 1 test run
rstmgr_cnsty_chk_test 32653671281645122706728066416272432155400803194881865655950479034811364165831 175
UVM_INFO @ 1784248993 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1802008993 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1819768993 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1837528993 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16