Simulation Results

Simulation Results: rv_dm/use_dmi_interface

12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.82 %

code
84.66 %

assert
96.90 %

func
96.90 %

block
94.01 %

line
94.58 %

branch
83.79 %

toggle
79.89 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		45.00%
V2S		94.00%
V3		5.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	48.000s	1485.425us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	42.000s	519.597us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	49.000s	656.162us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	63.000s	21342.823us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	45.000s	382.215us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	43.000s	9286.917us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	52.000s	3148.714us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	80.000s	62663.032us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	186.000s	108173.098us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	46.000s	499.144us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	46.000s	221.379us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	49.000s	385.287us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	36.000s	155.297us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	50.000s	466.621us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	40.000s	564.641us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	37.000s	101.019us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	52.000s	327.304us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	46.000s	499.144us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	35.000s	94.290us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	43.000s	807.063us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	49.000s	385.287us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	49.000s	98.636us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	42.000s	422.955us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	44.000s	194.381us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	71.000s	2248.858us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	57.000s	2204.554us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	44.000s	323.130us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	57.000s	2204.554us	1	1	100.00
	rv_dm_csr_rw	44.000s	194.381us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	35.000s	42.163us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	32.000s	39.419us	1	1	100.00

81/180 passed

45.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	48.000s	1485.425us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	43.000s	240.333us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	40.000s	630.059us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	42.000s	126.184us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	47.000s	589.266us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	70.000s	9285.430us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	49.000s	587.599us	0	20	0.00
bad_sba				1	20	5.00
	rv_dm_bad_sba_tl_access	54.000s	3866.148us	1	20	5.00
sba_autoincrement				2	20	10.00
	rv_dm_autoincr_sba_tl_access	170.000s	86351.006us	2	20	10.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	43.000s	526.529us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	54.000s	1957.663us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	38.000s	273.413us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	49.000s	59.921us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	52.000s	6202.385us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	90.000s	5162.992us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	36.000s	220.827us	1	1	100.00
stress_all				5	20	25.00
	rv_dm_stress_all	10802.265s	0.000us	5	20	25.00
alert_test				10	10	100.00
	rv_dm_alert_test	45.000s	106.178us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	50.000s	624.646us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	50.000s	624.646us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	57.000s	2204.554us	1	1	100.00
	rv_dm_csr_hw_reset	42.000s	422.955us	1	1	100.00
	rv_dm_csr_rw	44.000s	194.381us	5	5	100.00
	rv_dm_same_csr_outstanding	46.000s	100.592us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	57.000s	2204.554us	1	1	100.00
	rv_dm_csr_hw_reset	42.000s	422.955us	1	1	100.00
	rv_dm_csr_rw	44.000s	194.381us	5	5	100.00
	rv_dm_same_csr_outstanding	46.000s	100.592us	5	5	100.00

V2S

47/50 passed

94.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				28	30	93.33
	rv_dm_sec_cm	48.000s	855.178us	5	5	100.00
	rv_dm_tl_intg_err	50.000s	5824.463us	23	25	92.00
sec_cm_bus_integrity				23	25	92.00
	rv_dm_tl_intg_err	50.000s	5824.463us	23	25	92.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	54.000s	1957.663us	2	2	100.00
	rv_dm_debug_disabled	43.000s	120.964us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	54.000s	1957.663us	2	2	100.00
	rv_dm_debug_disabled	43.000s	120.964us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	48.000s	1485.425us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				9	10	90.00
	rv_dm_buffered_enable	46.000s	358.943us	9	10	90.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	43.000s	159.651us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	43.000s	159.651us	4	4	100.00
sec_cm_exec_ctrl_mubi				9	10	90.00
	rv_dm_buffered_enable	46.000s	358.943us	9	10	90.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	20	5.00
	rv_dm_stress_all_with_rand_reset	62.000s	6152.882us	1	20	5.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	192.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				42 test runs
	rv_dm_sba_tl_access	36171039515059661115766011700136049588348356873917078832632360272071876773682	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23816
	rv_dm_sba_tl_access	95622693772624181506156983056594055709103945761311902432357760606684497149944	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_autoincr_sba_tl_access	105594617532687426360846252518844085421656306809523762933734067569711137303303	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23919
	rv_dm_sba_tl_access	48133444011217852407004964042577499558654212558474449875177968039888113788059	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_autoincr_sba_tl_access	48091918453709999578869862511277741221857815593693606207197663030724480663479	153	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10068
	rv_dm_sba_tl_access	83783625839855472407197308216286615189241651694593579135545466608740491456241	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23806
	rv_dm_bad_sba_tl_access	87607347116611325741167508101125184473533543752815110981002609105937611518077	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23818
	rv_dm_autoincr_sba_tl_access	109838271705489347797166135543227952375124435556017229806501520605958172278835	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23806
	rv_dm_sba_tl_access	56069774228204343361075818007214695547912704750056348687646746412229459350952	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
	rv_dm_autoincr_sba_tl_access	49722498602638546749911395365277448269473369337293090254093682815147430927957	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23782
	rv_dm_sba_tl_access	2442102624738416260845879300559365979716624312192756300145617257054300255760	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23863
	rv_dm_autoincr_sba_tl_access	98447274907908797410156686674599317629715002501824001504730796917511068329344	159	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23909
	rv_dm_sba_tl_access	5163753902488149348816835536941913455716236959325818041779168979716398471631	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23807
	rv_dm_bad_sba_tl_access	8653013739690149861575080119807668862552302180202076592155595954364286411170	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23859
	rv_dm_sba_tl_access	75471214640727604201373692798170935803466198966844694581706930839683411985937	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23830
	rv_dm_autoincr_sba_tl_access	14805166080872687967951758286895453399669980957218771205606385786288021395431	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23877
	rv_dm_sba_tl_access	65634368274830500209464367714592847727653575634306713096326502719589176748270	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23808
	rv_dm_autoincr_sba_tl_access	38946917978044990301343556091789220247458056652453475542055096379035667878376	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_sba_tl_access	56846293835689769171297685406363970015085185348416107593439643707178797008080	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_sba_tl_access	54447077299709063658201706083824390637301364597471616611018376647799453704371	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_bad_sba_tl_access	40974577515515395242964056930931285784773492012436971695430032120940874349119	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_autoincr_sba_tl_access	27699180679997920062969543492329676420194626950475082752013814436548768397196	123	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23836
	rv_dm_sba_tl_access	59682397367345001733776280222699104667900747852454063010470721193354502851179	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23859
	rv_dm_bad_sba_tl_access	115408958824351602205770790440046247833920944169380912353917145199312879871351	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24277
	rv_dm_sba_tl_access	111664623764354644152865790858811092019416389705662707298965787846608030935368	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23873
	rv_dm_autoincr_sba_tl_access	9695557987847344728199626113761389929414269239244796394594601981519704723134	138	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23939
	rv_dm_sba_tl_access	87164027012179218973930668224996587552408405871119917057649858778117849942905	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_bad_sba_tl_access	106129745203215280250327342197063355899229404004622427904390941813819878303655	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10069
	rv_dm_autoincr_sba_tl_access	74123474075641027324151682511385461457862292451055261379406885013446006555539	168	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24006
	rv_dm_sba_tl_access	100887680167220809119869172100319302147129411265576037746113528518422053871353	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23882
	rv_dm_bad_sba_tl_access	22041411035018218446647380696966118884646760269824312259215312512531030696014	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23874
	rv_dm_sba_tl_access	108077079751817486220293804409651345485854813872642970457399732939778903727666	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23875
	rv_dm_delayed_resp_sba_tl_access	62747695290989886293304322838877514877441816811358075433066827078045012824351	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_autoincr_sba_tl_access	69366856047665468339965014916487528731782360399107551367103930883252666090139	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23960
	rv_dm_sba_tl_access	110052060687885791145998319493322612508364356423747566802096043687057928805023	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23866
	rv_dm_autoincr_sba_tl_access	59342197325948029362018676423290112287801984351133724387800994985284855925888	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_sba_tl_access	78601154171680463703976419915216687611599025804640357264950957569530971745590	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23873
	rv_dm_autoincr_sba_tl_access	8183896061918646457445059292227763398271508088829766923725014385827283365109	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23811
	rv_dm_sba_tl_access	81372143285660384084272047820118746220321306158365947354170332521608055736293	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23867
	rv_dm_bad_sba_tl_access	37390217328010700382361154665409328136484236356724762738371133027056255650115	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23955
	rv_dm_sba_tl_access	108283548994990233009082609111873476231977155823611487510066926066715641591379	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23873
	rv_dm_bad_sba_tl_access	15024800374599341420876133553575236605508765232404817425025147706859916030064	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23987
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				35 test runs
	rv_dm_delayed_resp_sba_tl_access	5419117297386253570049143673060634717716418803375573883412528929229135384304	107	UVM_INFO @ 365827571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	78847573310542100392674709434787116508238551026550754316421875839387819907745	107	UVM_INFO @ 142930535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	28917699877203194203213448181153295373705810249184315082070541797966306503888	107	UVM_INFO @ 205987580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	43482691072820433063119985322913651167157652789687082614641870127566562403999	107	UVM_INFO @ 127658320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	63231805229303284335979075364071533323378732723058077274385154231414343792185	107	UVM_INFO @ 149185592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	100038799359860092957817278779920846319768121505222234251307606564295675612690	107	UVM_INFO @ 251185211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	63681630260302501341892212716276401523312278065638474810995179768236155059072	107	UVM_INFO @ 302687039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	18191727675571136005106890097085554361436646202121393124797767828619123068643	107	UVM_INFO @ 587599433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	4349971172555325060431354803609143513966274262994808188713410355183666112036	107	UVM_INFO @ 666462285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	33726604030645885874772200390143185114711419849061391710520136607096640142813	107	UVM_INFO @ 612901087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	62787376008306304851890398766509749322020349921957022364119269498866306829880	107	UVM_INFO @ 96989180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	112780095437702271589284122249352298631370305355800519611726890239749725533651	107	UVM_INFO @ 542416131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	6787275619416098096339188946979839878137523555900428405647342762688846216374	107	UVM_INFO @ 90728428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	97362864371246018893473874400786267048000928257298610036392073079199035847998	107	UVM_INFO @ 471376838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	24525022079784267776233611640332060030980783809584234222385751295778618752262	107	UVM_INFO @ 253928282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	61699508919479259247537142185359108712295270879530706586370108851079709254388	107	UVM_INFO @ 50465073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	18267618763305019873754275893565922810604128309964833583317749483155591193222	107	UVM_INFO @ 84984293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	15213609311511560513073089709430600176811837967531390289063923352329671350850	107	UVM_INFO @ 104754167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	40049647152781770168312212116904473025589569598780623274047991009739491627963	107	UVM_INFO @ 99027668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	87159087352065913751337192895442002916896196671019128825786678028253554125318	107	UVM_INFO @ 95335138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	78313225519265440496466472796179979894220783316687886994440001686460845702935	107	UVM_INFO @ 573012934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	79116845835604586138914696373663923569929241436943038717657679856894238903465	107	UVM_INFO @ 262202708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	39954879571724043119746160187513822429308869760430599551387999069740698302060	107	UVM_INFO @ 250030616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	57844009527824034651894561703530818695726547362795377119589810403907557238368	107	UVM_INFO @ 534555147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	27531265336285995350672708774535543622052475258064625568500651931057507965139	107	UVM_INFO @ 312392529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	57987812270192191524933610670460870862348563446317340681185647205236580250697	107	UVM_INFO @ 273571044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	104326794212351079488357175423369007422185311117241633565500956214377928062068	107	UVM_INFO @ 968563082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	24944735687501254515479724942139535891906839114798018899635953889437620290619	107	UVM_INFO @ 72426130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	60861259532528507006366243701869158690038783651350010119002483297824312880704	107	UVM_INFO @ 1039859064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	104589001131936804389239210559865882038937063780043150071638153671860115700083	107	UVM_INFO @ 193568563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	66497314708080685184561703932014189391843172301509877188665075300293811992525	107	UVM_INFO @ 173317677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	10154169944235299826614076964801963134186919536685988711953939920949625689714	107	UVM_INFO @ 87557849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	57128935925252407298309323142696802980964151678497348772859318844873113326390	107	UVM_INFO @ 325148666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	35146869070905881888450290345904383897655062760729609567005282613729192293423	107	UVM_INFO @ 240388627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	85878356772192079146334045498919024312651334841545913296551957540084488072225	107	UVM_INFO @ 459529093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				12 test runs
	rv_dm_mem_tl_access_resuming	107947789508270594568403639861185900626912118535478410006991417714054510647692	87	UVM_INFO @ 155297146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	115596169291538142466503089219129996215141098655507867055709809869245572123616	87	UVM_INFO @ 61877276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	5868358155334458014680435626204150571431721954162744867147925219058193848669	88	UVM_INFO @ 167626203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	5747115280260804177318721318562644681311038566615545018249109390877651058030	91	UVM_INFO @ 363062566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	60185569436101020096991006002328916378822496993442160939331954526421906649011	95	UVM_INFO @ 5470526390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	94903466288020244353721614984214974579458173905775838848825800265299892317372	95	UVM_INFO @ 891530080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	51654310145934943846085422428467825040133543510706228119938591506953946064805	117	UVM_INFO @ 3041859663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72308375535934903281791164758314327157303299037080387194620518577393310451173	96	UVM_INFO @ 6389001190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	82603450017062020080072304756262295038305996323554888994051936873201516582471	91	UVM_INFO @ 166837184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	15482108768094113012193028543428923090248412596042342140313352266167057308363	114	UVM_INFO @ 2993137175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	84118639230018091445075930788078018731829989456643554364650881757858495415416	88	UVM_INFO @ 152311661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	80017910360639338497186010804717700345296356549186236622688551229916691677375	95	UVM_INFO @ 571801100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				12 test runs
	rv_dm_hart_unavail	92679264856520524404197247674639891137831679036125495679588841878187011036418	87	UVM_INFO @ 330257167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	52505539122502104922341469556624583247156562575256174500713670974816484322360	89	UVM_INFO @ 448866812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	25809565923366555591479634332007671918768215819695913699184761731790497878493	94	UVM_INFO @ 509756712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	11456557491480807750997825100326213057467501836945196090957063239749704197747	87	UVM_INFO @ 59920875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	60822176951148175087381800355564877828216251893282695733457275863067059248397	87	UVM_INFO @ 79435578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	104138253578882515828281760054615072701358050083376398249924483928085406126078	88	UVM_INFO @ 269724700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	52670717809996392737319434439431432739031420029923436921648386643405275500343	87	UVM_INFO @ 51021434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	100423266219640290739816692102800005866594374278502374837411025485098736487527	87	UVM_INFO @ 56891798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	24210520151267237072128920427479740428738885570265556362143440814564501681986	117	UVM_INFO @ 8124927171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45009943328884963635293053567140252492052449818094167713970781031104674548453	90	UVM_INFO @ 2653411010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	53491081643500850531138772815735975902140557542588566008787989795855615692005	126	UVM_INFO @ 6152882034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	89944196052717032126415356573284336598190463975661069292025855218708994765662	88	UVM_INFO @ 452540432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				11 test runs
	rv_dm_jtag_dmi_debug_disabled	64377857049564849468779154980623693923442492920726130892644366064638709743454	87	UVM_INFO @ 127699066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	5860598698083569359805785545632790206507969471028009177530239641810244791137	87	UVM_INFO @ 526528613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	103132492726753671854121147665860881065383482444925647642366125516918113727627	107	UVM_INFO @ 7325695636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	110226219118590746568431714383958126891010429350175304999380660342516727858380	117	UVM_INFO @ 1934893842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	58659103992455837760672583263988482955752933595173393337843060544711799159524	104	UVM_INFO @ 659955806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	78496430905560454089786431169029588825012822035070210771933931148405888665069	90	UVM_INFO @ 1819764839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	77590733992613828004646252330405876602347530786974835456162289177640739881515	101	UVM_INFO @ 854214189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	17550076374765690362189001050833185596722200589909183022175649972400987596390	88	UVM_INFO @ 367107444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	33373901402168611390062831561099278503160826838557975760707553256758187916588	111	UVM_INFO @ 1330556847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	29395787963596730931742267048993204963406930415233090579478001642005714034991	89	UVM_INFO @ 1734043732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	11530760041281043495018767419735670950581558118276227825672616572492754999520	98	UVM_INFO @ 460789757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				5 test runs
	rv_dm_stress_all_with_rand_reset	19912088646396279222590003364966865787724757648354694142502436961806580752434	97	UVM_INFO @ 1814752587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	75123599218247872233647367215239781471569036318628852649461950479335690183961	114	UVM_INFO @ 2358195354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	18118652423971109679241770864409887319876894060245287038719309602407042502448	113	UVM_INFO @ 6081193654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	96488460431031422225894989824881011018424099108913064594148001773897358217233	118	UVM_INFO @ 3125081778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	53401230846718676455672083735192135685313382111310473548616917320035424284395	96	UVM_INFO @ 711262640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				3 test runs
	rv_dm_scanmode	36829292368617291959767531179753970851935327575029679251448157868604051190978	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	16895305118636831354400397421914929639876181042820648740320876261511008131376	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72416639760304768014648313508294465343628555675523232079326615654738601842116	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [rv_dm_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	rv_dm_tl_intg_err	109519212553914435253931891062164016342143175916014850969574330274792718947210	99	UVM_INFO @ 338557582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tl_intg_err	32386385414790293488026493515340575793451749697668615631475467463140408364134	96	UVM_INFO @ 112283722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				1 test run
	rv_dm_buffered_enable	39626033775509077682787923248120051376702290050426442695357022438144020538959	89	UVM_INFO @ 194137083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	rv_dm_stress_all	39406356466537158317083823467776346107005943302334875575052641663190526368982	None