Simulation Results: rv_timer

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.98 %
  • code
  • 95.85 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
85.83%
V2S
100.00%
V3
27.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.000s 1031.557us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 16.685us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 2.000s 40.216us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 5591.775us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 21.751us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 85.675us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 2.000s 40.216us 5 5 100.00
rv_timer_csr_aliasing 2.000s 21.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 9.000s 33577.468us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 5.000s 3355.919us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 590.000s 509137.815us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 590.000s 509137.815us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 6.000s 2545.775us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 18.500us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 40.046us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 2084.256us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 2084.256us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 16.685us 1 1 100.00
rv_timer_csr_rw 2.000s 40.216us 5 5 100.00
rv_timer_csr_aliasing 2.000s 21.751us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 433.842us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 16.685us 1 1 100.00
rv_timer_csr_rw 2.000s 40.216us 5 5 100.00
rv_timer_csr_aliasing 2.000s 21.751us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 433.842us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 714.437us 5 5 100.00
rv_timer_tl_intg_err 3.000s 414.615us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 3.000s 414.615us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 10 10.00
rv_timer_min 6.000s 2044.593us 1 10 10.00
max_value 0 10 0.00
rv_timer_max 2.000s 199.639us 0 10 0.00
stress_all_with_rand_reset 10 20 50.00
rv_timer_stress_all_with_rand_reset 49.000s 35727.662us 10 20 50.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 27 test runs
rv_timer_min 29923320438556913505333859263108436998179997505882411087359883637845492894375 85
UVM_INFO @ 62686105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 64744601310442101949468717992678812478863015823914285872000066504475239606237 85
UVM_INFO @ 974139368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 37395312900054952291750617327923789924282651843767436651734924374870520948302 85
UVM_INFO @ 1191114958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 110306896213300051930717642772628368956622934258490722581674132919041852212777 84
UVM_INFO @ 161937964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 42956015859935665072427298990549234948629998894455850578317498456926471315901 85
UVM_INFO @ 124995343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 92870541168266093578710998987511073613314512170516743813220461609978054667565 84
UVM_INFO @ 299413886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 32958675792751954896874600951994760012434504658802318020155381244312974856035 86
UVM_INFO @ 130720315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 81723444903978654768099903426570643724035226463180134419934549356605643336867 85
UVM_INFO @ 561030144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 111814191222625779048806129813260204842531498697755151661579395188414031805951 84
UVM_INFO @ 1473743852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 101291447200819825903103398104334836488421520797859263426681619121872363492502 84
UVM_INFO @ 464615888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 78036720685180088147110718224452636469991028268104355179740446633845725189775 86
UVM_INFO @ 119762301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 83568875155684234860934850782723549880035961142634363171060767850689090323645 84
UVM_INFO @ 267816723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 65134339280817085643858900189798362273517707104028479852340225958320390622374 84
UVM_INFO @ 107129121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 80143524678567593314599387178943123626463402063105411508222737812196644670405 84
UVM_INFO @ 1092616010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 54531520181416445359329592602243644515945712680487099330750713369209324160137 84
UVM_INFO @ 675298933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 25892384093394942162701920038303277027310318056153863015203823520210926679575 85
UVM_INFO @ 2044592802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 96924034915162334204657868673167598813778878661554793189155907337224572095647 85
UVM_INFO @ 170921494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 108812810475069498776927513258337942962970745051007082918994010119273504016523 86
UVM_INFO @ 58576315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 91135743982144074944272679292627312189011219208581397395056628677867795445163 84
UVM_INFO @ 423086663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 33499783352309743394899173038096669444635061359808671320821438523077372516639 84
UVM_INFO @ 511314690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 112288670992349447048971649077499789810701404069035167763966860504852516305284 84
UVM_INFO @ 1688948048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 29366444697303725383041965108638283350531376126150351433067402401859453394043 84
UVM_INFO @ 79995798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 29551553930026148731447284824292977523524570761235975867781681871383033153021 84
UVM_INFO @ 77592388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 67842561665140649622742650857299002179645731019632149527218211325204965831313 87
UVM_INFO @ 852469204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 53433874392516410789238314154082792627229760563291698046236026862420027356055 85
UVM_INFO @ 1587415654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 87608681114285224068926761479225200194022263071841645656103648199903533003384 85
UVM_INFO @ 33577468465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 21738770606179205041681995137490040731160674906907424595725417609359340895467 84
UVM_INFO @ 110955936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 10 test runs
rv_timer_max 10676297972604025707023213466128010421147478827927838952115480949045766516740 84
UVM_INFO @ 199639475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 56437226848000832704768756166696289945624830499586477833244557474886964618144 85
UVM_INFO @ 46060831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 108880780746746307837984692972808892765193678011685959440761931697209287684779 84
UVM_INFO @ 45287495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 111446245394197073951281037501239956074498957378494644546914700514260169897266 84
UVM_INFO @ 186692866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 91179158790883757485080857197981271067442810918835848547320809126626653192828 84
UVM_INFO @ 89403807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 98074468000318985320536133130461137055656007371365343554209199825957237308689 84
UVM_INFO @ 174251920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 70317104125131071743812495211649262900230826969068041796441510011669497829005 84
UVM_INFO @ 86784941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 62335062831710725229973431666498496979900615973132483803892233230572076229535 84
UVM_INFO @ 334051378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 54048563653417234950149874287532702762821927630077741019006775270611431121804 84
UVM_INFO @ 71250175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 32574115926500082318875410461067778966051758478679690671317901235792232239520 84
UVM_INFO @ 47594846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 6 test runs
rv_timer_stress_all_with_rand_reset 65937675078217288569220710285494625600333547079832327975571430904879638922160 466
UVM_INFO @ 8627726788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 109859875408543621179086528085653971002211327115473566910496663883919898086811 207
UVM_INFO @ 8000724045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 95730448781373896793701361010645678059712559084872487202473994149510013283549 166
UVM_INFO @ 6816948901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 83850839339604067461599387405231308399811110828582776328584570307127787834724 265
UVM_INFO @ 2677155123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 108549573229014732598676179682560533706111271558131597142419721670837287304645 334
UVM_INFO @ 4244820154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 91504405891589890362248277927311315027277034730773066870763593414981766157311 268
UVM_INFO @ 2051755321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 4 test runs
rv_timer_stress_all_with_rand_reset 32629687556597544479096479209108463346620991850187307281264785061090906187033 139
UVM_INFO @ 1201834739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 28184318798071163170418524506403117602818564188088945388494435178947668684104 201
UVM_INFO @ 6821170270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 89056766100348309620847217260976770127909013498072421410032447940643878614750 218
UVM_INFO @ 9404865879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 78646576184172015275354344216055338690535577342222893559685005639423547957862 214
UVM_INFO @ 30463351461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---