Simulation Results: spi_host

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.13 %
  • code
  • 95.03 %
  • assert
  • 96.60 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 43.000s 1453.757us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 17.396us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 92.256us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 570.016us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 51.587us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 34.951us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 92.256us 5 5 100.00
spi_host_csr_aliasing 1.000s 51.587us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 36.550us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 21.554us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 64.315us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 5.000s 287.491us 10 10 100.00
spi_host_error_cmd 2.000s 19.457us 10 10 100.00
spi_host_event 168.000s 15230.054us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 164.653us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 164.653us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 164.653us 10 10 100.00
upper_range_clkdiv 4 5 80.00
spi_host_upper_range_clkdiv 954.000s 143062.320us 4 5 80.00
sw_reset 10 10 100.00
spi_host_sw_reset 36.000s 3721.877us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 30.701us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 164.653us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 164.653us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 43.000s 1453.757us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 43.000s 1453.757us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 17.000s 4110.908us 10 10 100.00
spien 10 10 100.00
spi_host_spien 86.000s 15561.087us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 757.000s 78025.891us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 21.000s 3134.608us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 5.000s 287.491us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 23.616us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 25.401us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 115.155us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 115.155us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 17.396us 1 1 100.00
spi_host_csr_rw 2.000s 92.256us 5 5 100.00
spi_host_csr_aliasing 1.000s 51.587us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 60.777us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 17.396us 1 1 100.00
spi_host_csr_rw 2.000s 92.256us 5 5 100.00
spi_host_csr_aliasing 1.000s 51.587us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 60.777us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 347.778us 25 25 100.00
spi_host_sec_cm 2.000s 105.951us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 347.778us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_upper_range_clkdiv 42946964552311260884005324587976851991065623494500793734739690651293909006057 181
UVM_INFO @ 143062319618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---