Simulation Results: ac_range_check

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.29 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.58 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
98.11%
V2
98.86%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 19 20 95.00
ac_range_check_smoke 58.000s 1871.221us 19 20 95.00
ac_range_check_smoke_racl 20 20 100.00
ac_range_check_smoke_racl 79.000s 2836.719us 20 20 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 88.975us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 21.593us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 43.000s 3182.514us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 28.000s 2161.868us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 111.335us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 21.593us 5 5 100.00
ac_range_check_csr_aliasing 28.000s 2161.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 63.022us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 50.000s 483.148us 1 1 100.00
stress_all 9 10 90.00
ac_range_check_stress_all 259.000s 18022.115us 9 10 90.00
alert_test 10 10 100.00
ac_range_check_alert_test 32.000s 37.841us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 20.394us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 6.000s 372.177us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 6.000s 372.177us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 3.000s 88.975us 1 1 100.00
ac_range_check_csr_rw 3.000s 21.593us 5 5 100.00
ac_range_check_csr_aliasing 28.000s 2161.868us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 656.550us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 3.000s 88.975us 1 1 100.00
ac_range_check_csr_rw 3.000s 21.593us 5 5 100.00
ac_range_check_csr_aliasing 28.000s 2161.868us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 656.550us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 4210.394us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 4210.394us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 4210.394us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 4210.394us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 133.000s 5116.730us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 12.895us 5 5 100.00
ac_range_check_tl_intg_err 13.000s 398.478us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 330.000s 2429.790us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 53.000s 3262.943us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 2 test runs
ac_range_check_stress_all 77286145503632678852422916471407382915836943292368535652492114188563408100667 4413
UVM_INFO @ 2770404660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 45595645027770395047572407716505072080424359335211609098798192864122373312273 4518
UVM_INFO @ 488237881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---