| V1 |
|
100.00% |
| V2 |
|
88.76% |
| V2S |
|
98.05% |
| V3 |
|
60.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 43.640s | 456.041us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 9.350s | 301.083us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 11.320s | 144.907us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 278.650s | 13165.007us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 349.900s | 4781.513us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 16.320s | 210.908us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 11.320s | 144.907us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 349.900s | 4781.513us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 386.480s | 69834.740us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 107.450s | 1616.673us | 50 | 50 | 100.00 | |
| entropy | 22 | 25 | 88.00 | |||
| alert_handler_entropy | 3600.138s | 0.000us | 22 | 25 | 88.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 98.800s | 4918.382us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 43.640s | 456.041us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 75.880s | 4964.757us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 93.280s | 5262.204us | 50 | 50 | 100.00 | |
| ping_timeout | 21 | 50 | 42.00 | |||
| alert_handler_ping_timeout | 599.190s | 226126.264us | 21 | 50 | 42.00 | |
| lpg | 96 | 100 | 96.00 | |||
| alert_handler_lpg | 3600.130s | 0.000us | 49 | 50 | 98.00 | |
| alert_handler_lpg_stub_clk | 3600.136s | 0.000us | 47 | 50 | 94.00 | |
| stress_all | 49 | 50 | 98.00 | |||
| alert_handler_stress_all | 4884.380s | 447252.448us | 49 | 50 | 98.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 37.560s | 3464.687us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 6.570s | 246.156us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.510s | 10.593us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 40.450s | 8469.352us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 40.450s | 8469.352us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 9.350s | 301.083us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 11.320s | 144.907us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 349.900s | 4781.513us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 51.150s | 736.131us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 9.350s | 301.083us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 11.320s | 144.907us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 349.900s | 4781.513us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 51.150s | 736.131us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 435.320s | 57094.118us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 435.320s | 57094.118us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 435.320s | 57094.118us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 435.320s | 57094.118us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1265.860s | 15967.311us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 92.380s | 14058.346us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 92.380s | 14058.346us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 435.320s | 57094.118us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 43.640s | 456.041us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 43.640s | 456.041us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 43.640s | 456.041us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 43.640s | 456.041us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 98.800s | 4918.382us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 49 | 50 | 98.00 | |||
| alert_handler_lpg | 3600.130s | 0.000us | 49 | 50 | 98.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 98.800s | 4918.382us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 22 | 25 | 88.00 | |||
| alert_handler_entropy | 3600.138s | 0.000us | 22 | 25 | 88.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 22 | 25 | 88.00 | |||
| alert_handler_entropy | 3600.138s | 0.000us | 22 | 25 | 88.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.270s | 781.687us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 6 | 10 | 60.00 | |||
| alert_handler_stress_all_with_rand_reset | 201.640s | 2094.323us | 6 | 10 | 60.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 23 test runs | |||
| alert_handler_ping_timeout | 7870273008337608989885330529780201825294725870343999678324426391416101251192 | 108 |
UVM_INFO @ 16485449496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 16537146646418129087898402052353394225255086481614581796194634372225141831099 | 126 |
UVM_INFO @ 16490418050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 45534749095327601735037295289828914366985195797043730659804083514507205325457 | 105 |
UVM_INFO @ 9566951542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 104141905144103365214366904573529734178790169034913024730004049257197600332905 | 114 |
UVM_INFO @ 11128168854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 76639150150337933612916471684035417225609268364313521992120016446389102576888 | 145 |
UVM_INFO @ 17952850954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 45339377424058868038393971846201138934775384341444455842254448965080213506975 | 96 |
UVM_INFO @ 22402192713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 108996086226732997641895670451472330982501545497486995102779527263392559615207 | 90 |
UVM_INFO @ 5993252317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 16222900106298450085235407263786607918418342047503898168836292391328832428516 | 129 |
UVM_INFO @ 90917449879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 11985748342892012135373792889351942075389671191633011672418290537421236553353 | 103 |
UVM_INFO @ 2802242027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 81684028672549671338755787089376668545322427385635263382445313158753881168613 | 150 |
UVM_INFO @ 13196960302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 55455799388548785993532686452450008317536446035573691785830809670345096505906 | 97 |
UVM_INFO @ 4865053320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 83338296252488173302469037755753725089800538768365522235893275433421839031309 | 130 |
UVM_INFO @ 8487610988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 85872691016136214683363786767354683763798096054246711675181581577662963378144 | 145 |
UVM_INFO @ 10747051491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 99615556391363243230819927553296053296844664646164841678210435235777447412691 | 97 |
UVM_INFO @ 2887601798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 42941706096267887811156892252703660432899187177652118206674511109341849578413 | 92 |
UVM_INFO @ 2069972242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 23243454733523976119830806103589389887148297079511251209395688807071989575684 | 87 |
UVM_INFO @ 991992746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 93132887340774386951157532018367114213131572070014262068555615002746322769009 | 90 |
UVM_INFO @ 6983738046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 74309950269417583729123425404867847825816806784687047023468500158341863112615 | 100 |
UVM_INFO @ 5630105389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 38715552940840685350942564009065417992302652446472285946515075563572777351218 | 105 |
UVM_INFO @ 15231790839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 31229594163955981322215919049578426486007503297250401627167523136905727367924 | 85 |
UVM_INFO @ 1663358446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 77779545937240805572983259757639109105946358911724636152214892010231898513481 | 135 |
UVM_INFO @ 33655662205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 102932192591305767769599317678137331085074371711162607434050684978581954750361 | 138 |
UVM_INFO @ 84477876379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 101199167995149266658442743512941620074980980986722046902684922924212692010788 | 123 |
UVM_INFO @ 9818077757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 106066780603240751453050991107735235774260037636501719604364122585774280814963 | 218 |
UVM_INFO @ 119797539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 36104581029105198924138582792247842189352531338633309570186731343446503485904 | 214 |
UVM_INFO @ 187704098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 22516147118749260127212933390907137225122549195005941363502160856832821232861 | 220 |
UVM_INFO @ 568325969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 3910142566646414876793577137363961612003328966751440890163317025761467111994 | 168 |
UVM_INFO @ 123251870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 33063603207936998109473926569259505796883356535589094644208639224100401425102 | 154 |
UVM_INFO @ 103073319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 79847228938825738622013859369645151295857220241922097218918101775660499664568 | 140 |
UVM_INFO @ 621376354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 4636701291971150758957306678592644771853851671440917560022467181153301426762 | 166 |
UVM_INFO @ 192472244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 14834745369536605212995331829694625056668526832929040178203777828244866646667 | 150 |
UVM_INFO @ 200162728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 96348728495805399160641012709925981254286222333515080785183260322954609249271 | 142 |
UVM_INFO @ 1266772229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 59955333972067818098130086998524402738131745707339149933081900725388854566050 | 178 |
UVM_INFO @ 313957974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 63239581678867597943303715825176282319220040208230602135367763141405143192671 | 180 |
UVM_INFO @ 1405955131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 15439531261432965018997899015295315068848793024910035057517320290594402659333 | 202 |
UVM_INFO @ 304499865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 9532369188260633870781019982147997542529791131365484689327576008655447227747 | 218 |
UVM_INFO @ 3464687342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 42138070973888105388842823869315273607592399481219856167053969057794668657754 | 218 |
UVM_INFO @ 1135296879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 39392438354807611456596080452216079809034370538169835635032285809256549697743 | 222 |
UVM_INFO @ 511750366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 70109532199780602326830730976053903775804471112181869846732452323284329205709 | 200 |
UVM_INFO @ 233536906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 87835949810911587740093967354671286958370571042705194958184042501298538123520 | 220 |
UVM_INFO @ 148069835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 50589387932185025042008320029843661906945469002190076193080781819562963208924 | 162 |
UVM_INFO @ 389088127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 109034862267693928212093934680935194188215914149285497259953046096172454924675 | 224 |
UVM_INFO @ 249409653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 102017597299577541219055479750306219887249841018025046294780854556389779480164 | 176 |
UVM_INFO @ 79697335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 6 test runs | |||
| alert_handler_lpg_stub_clk | 94912811271525283850437703312025146201991979910256370664039531174297617839790 | None | ||
| alert_handler_lpg_stub_clk | 107197032465742487508489468821995745849809694791186420115597652463780814470229 | None | ||
| alert_handler_entropy | 33501858507316729948771265062510766389871805093258727838558221406677495904245 | None | ||
| alert_handler_entropy | 91549795640133337271998307245673972298099107551168228120243509901975443139129 | None | ||
| alert_handler_lpg_stub_clk | 48896452087868590019459962612729980660566244990858714664019968938457889891466 | None | ||
| alert_handler_lpg | 97156297639000219737203112498722315767185074336668137255840878989145905949339 | None | ||
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 6 test runs | |||
| alert_handler_ping_timeout | 108856892752582355763172834553839081008036243597369572914973707298167867389629 | 80 |
UVM_INFO @ 1591618679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 5098178218178852870098510676780437927351428902277834541682797312883541672779 | 80 |
UVM_INFO @ 225318237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 70145671509262316414075170254996652510720665902385734985594205355223846210663 | 80 |
UVM_INFO @ 273916383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 23110801715892184372322796627663817893468885407885094864374932579877482360489 | 80 |
UVM_INFO @ 1449827881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 22658280957166205746542513588961184069617883566589633085108978083633463310003 | 80 |
UVM_INFO @ 516921094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 20657992957476435969790387299699265469308707696125160374348081007730363020936 | 80 |
UVM_INFO @ 179469357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 4 test runs | |||
| alert_handler_stress_all_with_rand_reset | 75381953429945950875411466079168723702686624733914997506071995626569077329074 | 110 |
UVM_INFO @ 4170964558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 28191357542037045372803375199402240400028062055891601633769117324170163015026 | 93 |
UVM_INFO @ 1475367275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 114392525931974866554489290809163508123958700567083829477715930354250564929236 | 133 |
UVM_INFO @ 4052639422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 78921225137803153070966414441755359625690093825065687506256101461600551361156 | 117 |
UVM_INFO @ 5993191009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_entropy | 70269889820608035106070371532704844747662098766146694147436520929140529413458 | 80 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 1 test run | |||
| alert_handler_stress_all | 31861651426301623800311136829923459535251691566693429670870489029676016048399 | 375 |
UVM_INFO @ 306227179237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|