| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 2.000s | 645.750us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 3.000s | 787.767us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| aon_timer_csr_rw | 2.000s | 462.825us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 10.000s | 6160.027us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 8.000s | 424.781us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 2.000s | 594.782us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| aon_timer_csr_rw | 2.000s | 462.825us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 8.000s | 424.781us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 2.000s | 489.670us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 1.000s | 478.301us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 92.000s | 62094.076us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 3.000s | 598.983us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 158.000s | 122970.337us | 15 | 15 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| aon_timer_alert_test | 21.000s | 446.013us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| aon_timer_intr_test | 2.000s | 528.906us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| aon_timer_tl_errors | 4.000s | 418.698us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| aon_timer_tl_errors | 4.000s | 418.698us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 3.000s | 787.767us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 2.000s | 462.825us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 8.000s | 424.781us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 8.000s | 2282.162us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 3.000s | 787.767us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 2.000s | 462.825us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 8.000s | 424.781us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 8.000s | 2282.162us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| aon_timer_sec_cm | 17.000s | 7653.741us | 5 | 5 | 100.00 | |
| aon_timer_tl_intg_err | 20.000s | 8721.284us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| aon_timer_tl_intg_err | 20.000s | 8721.284us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 3.000s | 571.112us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 2.000s | 491.443us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 9.000s | 3234.306us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 3.000s | 587.470us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 34.000s | 3952.366us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 41.000s | 18377.607us | 15 | 15 | 100.00 | |