Simulation Results

Simulation Results: clkmgr

19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
78.38 %

code
70.05 %

assert
90.29 %

func
74.80 %

line
82.42 %

branch
87.53 %

cond
80.31 %

toggle
100.00 %

FSM
0.00 %

Validation stages

V1		65.22%
V2		69.23%
V2S		26.67%
V3		0.00%

15/23 passed

65.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	1.900s	61.085us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.430s	35.208us	1	1	100.00
csr_rw				2	5	40.00
	clkmgr_csr_rw	1.370s	33.068us	2	5	40.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	1.720s	21.181us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.940s	63.288us	1	1	100.00
csr_mem_rw_with_rand_reset				1	5	20.00
	clkmgr_csr_mem_rw_with_rand_reset	2.170s	63.305us	1	5	20.00
regwen_csr_and_corresponding_lockable_csr				3	6	50.00
	clkmgr_csr_rw	1.370s	33.068us	2	5	40.00
	clkmgr_csr_aliasing	1.940s	63.288us	1	1	100.00

81/117 passed

69.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.780s	55.928us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	3.510s	159.156us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	2.940s	169.471us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	1.900s	61.085us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.360s	29.011us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.000s	9.461us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.360s	29.011us	0	10	0.00
stress_all				1	10	10.00
	clkmgr_stress_all	3.110s	139.126us	1	10	10.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.970s	73.869us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	13.100s	870.315us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	13.100s	870.315us	25	25	100.00
tl_d_outstanding_access				5	12	41.67
	clkmgr_csr_hw_reset	1.430s	35.208us	1	1	100.00
	clkmgr_csr_rw	1.370s	33.068us	2	5	40.00
	clkmgr_csr_aliasing	1.940s	63.288us	1	1	100.00
	clkmgr_same_csr_outstanding	2.040s	73.283us	1	5	20.00
tl_d_partial_access				5	12	41.67
	clkmgr_csr_hw_reset	1.430s	35.208us	1	1	100.00
	clkmgr_csr_rw	1.370s	33.068us	2	5	40.00
	clkmgr_csr_aliasing	1.940s	63.288us	1	1	100.00
	clkmgr_same_csr_outstanding	2.040s	73.283us	1	5	20.00

V2S

28/105 passed

26.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				1	30	3.33
	clkmgr_sec_cm	138.660s	10016.925us	1	5	20.00
	clkmgr_tl_intg_err	8.080s	547.051us	0	25	0.00
shadow_reg_update_error				15	20	75.00
	clkmgr_shadow_reg_errors	2086.520s	200000.000us	15	20	75.00
shadow_reg_read_clear_staged_value				15	20	75.00
	clkmgr_shadow_reg_errors	2086.520s	200000.000us	15	20	75.00
shadow_reg_storage_error				15	20	75.00
	clkmgr_shadow_reg_errors	2086.520s	200000.000us	15	20	75.00
shadowed_reset_glitch				15	20	75.00
	clkmgr_shadow_reg_errors	2086.520s	200000.000us	15	20	75.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	2.350s	93.885us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	8.080s	547.051us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.360s	29.011us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.000s	9.461us	0	10	0.00
sec_cm_meas_config_shadow				15	20	75.00
	clkmgr_shadow_reg_errors	2086.520s	200000.000us	15	20	75.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	3.150s	138.280us	10	10	100.00
sec_cm_jitter_config_mubi				2	5	40.00
	clkmgr_csr_rw	1.370s	33.068us	2	5	40.00
sec_cm_idle_ctr_redun				1	5	20.00
	clkmgr_sec_cm	138.660s	10016.925us	1	5	20.00
sec_cm_meas_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.370s	33.068us	2	5	40.00
sec_cm_clk_ctrl_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.370s	33.068us	2	5	40.00
prim_count_check				1	5	20.00
	clkmgr_sec_cm	138.660s	10016.925us	1	5	20.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.590s	42.819us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	42.780s	2487.452us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				29 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	87231192214960148572116756367932796132175382572883391026059825453043850093490	75	UVM_INFO @ 5831658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	104816587900171613804807101918457329077220404003165433970759207804465709834170	82	UVM_INFO @ 5310027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	42669297573899064562132971964481156088918190070741460522868041841833763937272	75	UVM_INFO @ 3810250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	42517821407485579181528322743647645677168011947169668961890841851594580697195	75	UVM_INFO @ 5938401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	77698420243531633026822692946626406810647424041661180248633155742869998549947	82	UVM_INFO @ 11808817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	58612653982106481915930508846862471139812528153283741477259719281832623838093	86	UVM_INFO @ 47692018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	65038974229956270756276692742197332020434676093613983478194680031307138306451	75	UVM_INFO @ 3832841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	41754803271245437119836370282957400300617850019354759608363056748850416714165	75	UVM_INFO @ 7347659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	79431487506682802022686734379475593402427759708006892442613404183249928939605	89	UVM_INFO @ 13946439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	79135836482678353104766064170401916301925789116148429112721218434556138372161	75	UVM_INFO @ 10470853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	110416724580548068090170118150178214899227788900935563553831638237387740654332	75	UVM_INFO @ 5517534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	101856691853908877393242635539020284844406992736598734742007532348445398552792	75	UVM_INFO @ 18688227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	28438797707997486862429308604332905511984700531748978725235204823692747308199	75	UVM_INFO @ 8116527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	100947725349364844859552226298264849667572150779463890434308674694339863908508	75	UVM_INFO @ 5612395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	86137788189671802254362365480910198729480748683912456136562313015968448731002	75	UVM_INFO @ 18853772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	25215487154878393839418765666970475512922933447813972172787323894648032654670	82	UVM_INFO @ 10273229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	12713339466258409105635701890921052271829461764340853722640785277532829470126	75	UVM_INFO @ 3770713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	15960638070314779361572339121134300148829961369639124435964053731360995219919	86	UVM_INFO @ 14878150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	35368043848897971990821197339460612181851356197850617534075571923083129881894	75	UVM_INFO @ 57928702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	46575268339780640825442229630874780039513650392910112552016512223545463170771	85	UVM_INFO @ 4486907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	38446721332831645658427853449802333150280132208210901134148036790530827289599	82	UVM_INFO @ 11065484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	65357261410016127172916285233185188724293452734827057692383403910866309566059	75	UVM_INFO @ 93885263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	6372274477763363732920106941464704494629396754414437647189376104328634317227	75	UVM_INFO @ 9493208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	41208522972477145179171145058612610882265706188377286510390162725938342444971	85	UVM_INFO @ 4084376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	82459946386674966100241421075720111210793439381298015007159271594600348949027	75	UVM_INFO @ 4487808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	77648610575565314107316340340899216420067920255851758771949406943893655005618	78	UVM_INFO @ 4013556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	77587135386811249863166616359978393576026479823843913489197918160937071354095	86	UVM_INFO @ 6706270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	968590500204088631237232989166418010745471904341425942984742243376233233701	114	UVM_INFO @ 43353265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	76411797150097330641241010102105827308776175953405639994686031909536759220364	85	UVM_INFO @ 3502615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				23 test runs
	clkmgr_tl_intg_err	40758945698489256053949556870931505555008167098252417464655253261814533149384	93	UVM_INFO @ 14102556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	35189365270552113834467989909047424824046530544978446808776666175154589407794	75	UVM_INFO @ 3570714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	101829357408415131039747995029894986783766610616243249124821196219458394099982	76	UVM_INFO @ 1953246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	94323960393669062663582901074513084904285013242078628762051751518027838953343	82	UVM_INFO @ 63305422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	37627532012030787248474752128348059457542878001187365340350670447824748986660	113	UVM_INFO @ 547051200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	110821380098091840946445413933984189140934263589281767459215596425135578152310	76	UVM_INFO @ 10205830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	108870311016182506327727845478468237173296552661457162398028544635752757972202	76	UVM_INFO @ 13511483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	76533923413732557936302124060011295181331299443025477347991303379215007614560	75	UVM_INFO @ 45174617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	477201735276105355640106631872441336972745700081414818605279161935595789198	94	UVM_INFO @ 186672853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	63977718155827043301835213270871830338768953673430624742995360214417808062159	86	UVM_INFO @ 9377208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	36455367411643238414714925769785501278514354072203172025566683662001037132383	85	UVM_INFO @ 5479990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	88701511117165892683473598679129156689406781348989323721099397168948591142063	78	UVM_INFO @ 3446596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	108692548805015381091268542806753217944169424741412741886831877940625904702216	78	UVM_INFO @ 5018575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	105084528282294521440571189795269334583104425147475488367215245935492059300360	75	UVM_INFO @ 5674101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	42756721834009208689235535851765736477473368788295702864657437754131007806268	104	UVM_INFO @ 14168977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	66320885941156187456208457228918452612922928772555620882770750191303408070259	75	UVM_INFO @ 4286020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	80561611391556700856772976811765545005990349631262241621573109883325246099216	78	UVM_INFO @ 4613051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	41173264873775331483055387092239903148608940936426889340194178224987475824148	82	UVM_INFO @ 1850381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	6438095058781352483121091640499963358320573214115297195249822049813793572793	75	UVM_INFO @ 23057537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	91469234849724389299501574860945365792194795033342702377053387226762285679666	75	UVM_INFO @ 7713921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	76370584763021090724112539229751026502723797557811268788869667435495469230228	93	UVM_INFO @ 24259589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	83482059534611640350508540503862007763838020817480680184221076341195035072083	86	UVM_INFO @ 12027333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	107392922203712439293716151024043721591821395779584496506211021018993151270734	89	UVM_INFO @ 8306062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				22 test runs
	clkmgr_frequency_timeout	61912228138829427581373970842636440595738234915022372786047148921509230296641	77	UVM_INFO @ 4710004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	68250386273995123497269145435481079982883407731531284163286647411776759140558	93	UVM_INFO @ 2487451769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	867837322023432214284069375352171164651308962284028763928927766892850637528	77	UVM_INFO @ 14576790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	38092903961191246487953032623363133228365851312363403324222792868049162817870	78	UVM_INFO @ 2520747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	110464223368368332110835799150768612662822303318503434242094952094753035281921	79	UVM_INFO @ 7029661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	18077177304637590458485484656215760557244824669897654608661111279418387429886	78	UVM_INFO @ 9526367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	31917970508367327732839055993383963312138888890741673640808231214659040990659	78	UVM_INFO @ 9460923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	77854475959949233069462706066979923324722846360772307884127646738780953235032	77	UVM_INFO @ 4296512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	32046236752246042876118978188517215314432811685968609903400727467565638691184	89	UVM_INFO @ 16981074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	103723768682535220019831968604548709813413503041639268701849514964138355569372	78	UVM_INFO @ 3833875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	16017198604030490422378452434519914012456038082790493712036906653109329349326	155	UVM_INFO @ 1216904137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	25338101431838606434183266346384868785450146761646015273039932738556327285043	77	UVM_INFO @ 139126047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	65368464737051936008636506175865131520038183135574310822109510423091868883115	78	UVM_INFO @ 6174969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	6044785760293346525300305937594778684291543357196808677740495962143224678781	77	UVM_INFO @ 4856761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	27903780372669439326495165485458791010651980816930668984939911896934849776369	77	UVM_INFO @ 3546083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	12030628034953750686342490310068273372529304094324019492548119779681590609583	161	UVM_INFO @ 157920032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	75276715161312652929871065381948990216428417793509472133988468894415811059565	78	UVM_INFO @ 3748959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	41547212947173143705126536757572915052713994081006621063473077533228093907395	79	UVM_INFO @ 5754578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	31161654880935023236673006189822074560058916806825070520129562207487804818973	77	UVM_INFO @ 2777172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	20708023282080912790134224844611792079475905316661022042006040345762590428233	113	UVM_INFO @ 127078030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	79254672028992614492327701608478910453449571159361857229705208803901246895820	78	UVM_INFO @ 7429755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	103705969587247992533054447530778438629265496734899404672023334497455495134225	78	UVM_INFO @ 3945512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				17 test runs
	clkmgr_frequency	47526704625635188370027654338839275390365940271939956032040300986205405618949	76	UVM_INFO @ 7812429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	42370250317725626947119165506655135591708540145400409792618103324006052914007	75	UVM_INFO @ 5741029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	17150261937532455038894049080078340994184807027539854024580734841839775605304	76	UVM_INFO @ 6466202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	8930904042230107671173120617041973340007023824644764232766219346028778796651	90	UVM_INFO @ 151426872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	111504270049891995031722563318489125459670156450926421141463370437230603997489	77	UVM_INFO @ 11122515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	37989445139998279955223973288758151717010090966779911480411981691767240123745	75	UVM_INFO @ 29011166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	57956443490299088089719173783802546299021215069842369483900655321961617020003	80	UVM_INFO @ 18360045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	109179339611790359173807359602980440634510480616008160297667606358423084161744	76	UVM_INFO @ 5586538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	73463620374612542216594509714647399381476093387139084333524446127246058157648	76	UVM_INFO @ 7644940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	62973557377166672866767504204785440150719681498378209948905741168379822998676	77	UVM_INFO @ 10228709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	111149472277725907384497066800364897634819814883448039762633990659118362987301	75	UVM_INFO @ 23925737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	98935670668588531240510677377162783948128271238052079183260099319276877688173	76	UVM_INFO @ 13111824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	114180030914292009713629560598547163874514163290791032031176113427571516006944	76	UVM_INFO @ 12898156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	112947307421865256673133555835330599003161279197652900309277234254249687552082	76	UVM_INFO @ 6672581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	109839170100333564934095264426480663691792313330202112363955646296673476924363	92	UVM_INFO @ 110273134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	5600558239809004660216338486149112241387747407703899353034762507148740900349	76	UVM_INFO @ 6638553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	18274790486147372306345381311351518434562993597493370616411947156253605767614	145	UVM_INFO @ 43154990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				6 test runs
	clkmgr_regwen	22395304299862998421595938881099212230739298867871526173938347320202614392263	74	UVM_INFO @ 4793331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	96740363486855189410608156178659078801814713734798022606638896168034045707124	74	UVM_INFO @ 5060783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	78403250896427456677595283246799880445124531611045304306200365601807605634708	74	UVM_INFO @ 6745797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	43857682017408851504758304113120712421883498362992526372739678946188717151320	74	UVM_INFO @ 42818811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	97755735629071118648469358569438654298335043009038453039944262746087533092293	74	UVM_INFO @ 2414521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	73108734505931586688993833918820242996218879584807318537793411996957133514429	74	UVM_INFO @ 7611453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				5 test runs
	clkmgr_shadow_reg_errors	55891115580216358534801176897581751091666998874044897632834306343580532350981	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	8490243709297521199650687423312477698984694739490888530890022663887874988888	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	80586941261548045964418859056780275207327804369225835384705508946382242931769	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	111393788786591191182805761994105383283424316481549883880924066796913586579259	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	19895742948968835999574116138268426794028837257298385497967548268824294449975	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				4 test runs
	clkmgr_same_csr_outstanding	86826344274323308157117124191245171113313697514888623631932872294492719329274	75	UVM_INFO @ 58406201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	61863798311233780293550971064085975132268136960407497817059596328678986383168	75	UVM_INFO @ 10000285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	110303036091590550525453879474487643990508280737860732166706323828482667347211	75	UVM_INFO @ 10405781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	18059049412522173271136915497779156634099813317725652078325159384985640998767	75	UVM_INFO @ 8700814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				3 test runs
	clkmgr_sec_cm	24092759534397224383224128784109135351274656829719957136488898102337609898435	80	UVM_INFO @ 10005691560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	12750552018728769632183278301042007465279384750867047587560654106113629280397	87	UVM_INFO @ 10016925318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	78958749638521747997061089943105558729810440085147385600371924001314834916769	125	UVM_INFO @ 10251195333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				3 test runs
	clkmgr_regwen	93776427854825416150647527264290164489486054491515585561471332547897541846716	74	UVM_INFO @ 7463334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	97202895075706046905395240026370484911268540998320578631177961439458268420941	74	UVM_INFO @ 4374813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	6274726835969055445312408665656744608829632254338801399741711834735873605954	74	UVM_INFO @ 4139342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				1 test run
	clkmgr_sec_cm	36509952493964780995514654576641077391627086985019097290326825147946865129588	124	UVM_INFO @ 54152759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	88706642565345686169078592046106973421590122126553525540886858376813083091436	75	UVM_INFO @ 21180838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en				1 test run
	clkmgr_regwen	6857958890990439866500543089286094779200997850568789005459602480635574012473	74	UVM_INFO @ 4068522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---