Simulation Results

Simulation Results: csrng

19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.61 %

code
96.17 %

assert
97.16 %

func
90.50 %

block
98.49 %

line
99.50 %

branch
96.30 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		97.37%
V2		98.09%
V2S		98.68%
V3		0.00%

37/38 passed

97.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	4.000s	77.665us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	33.000s	30.797us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	11.000s	23.014us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	60.000s	1350.317us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	37.000s	291.886us	1	1	100.00
csr_mem_rw_with_rand_reset				4	5	80.00
	csrng_csr_mem_rw_with_rand_reset	257.000s	10015.055us	4	5	80.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	11.000s	23.014us	5	5	100.00
	csrng_csr_aliasing	37.000s	291.886us	1	1	100.00

1282/1307 passed

98.09 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	73.000s	5840.587us	500	500	100.00
err				500	500	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
cmds				2	25	8.00
	csrng_cmds	320.000s	30315.034us	2	25	8.00
life cycle				2	25	8.00
	csrng_cmds	320.000s	30315.034us	2	25	8.00
stress_all				23	25	92.00
	csrng_stress_all	761.000s	60788.598us	23	25	92.00
intr_test				10	10	100.00
	csrng_intr_test	3.000s	82.933us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	33.000s	30.567us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	18.000s	723.814us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	18.000s	723.814us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	33.000s	30.797us	1	1	100.00
	csrng_csr_rw	11.000s	23.014us	5	5	100.00
	csrng_csr_aliasing	37.000s	291.886us	1	1	100.00
	csrng_same_csr_outstanding	5.000s	183.473us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	33.000s	30.797us	1	1	100.00
	csrng_csr_rw	11.000s	23.014us	5	5	100.00
	csrng_csr_aliasing	37.000s	291.886us	1	1	100.00
	csrng_same_csr_outstanding	5.000s	183.473us	5	5	100.00

V2S

1268/1285 passed

98.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				29	30	96.67
	csrng_sec_cm	10.000s	852.254us	5	5	100.00
	csrng_tl_intg_err	387.000s	13167.267us	24	25	96.00
sec_cm_config_regwen				16	30	53.33
	csrng_regwen	3.000s	62.291us	11	25	44.00
	csrng_csr_rw	11.000s	23.014us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	73.000s	5840.587us	500	500	100.00
sec_cm_intersig_mubi				23	25	92.00
	csrng_stress_all	761.000s	60788.598us	23	25	92.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
	csrng_sec_cm	10.000s	852.254us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
	csrng_sec_cm	10.000s	852.254us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
	csrng_sec_cm	10.000s	852.254us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
	csrng_sec_cm	10.000s	852.254us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
	csrng_sec_cm	10.000s	852.254us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	73.000s	5840.587us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
sec_cm_constants_lc_gated				23	25	92.00
	csrng_stress_all	761.000s	60788.598us	23	25	92.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	73.000s	5840.587us	500	500	100.00
sec_cm_tile_link_bus_integrity				24	25	96.00
	csrng_tl_intg_err	387.000s	13167.267us	24	25	96.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
	csrng_sec_cm	10.000s	852.254us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00
	csrng_sec_cm	10.000s	852.254us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	20.000s	1071.722us	200	200	100.00
	csrng_err	7.000s	71.742us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3600.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				19 test runs
	csrng_cmds	63028097293158463976948600610273386917872304465349024668607804913655778076426	100	UVM_INFO @ 266081020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	108980394612514275932871987988863820809546323305580688480165524156232909340654	100	UVM_INFO @ 49807152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	80394638401397562333979105478096457302853855435815628570117851281227389291647	100	UVM_INFO @ 338056375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	96409181733675174094495762961386678828027852405830223519915579074811332182326	100	UVM_INFO @ 34499236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	55466984141070049642954487083367144589294353636015957017975951568312350212605	110	UVM_INFO @ 41151691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15926909856701772410094091289424068330428001139577557067174934853032957145669	100	UVM_INFO @ 34401319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	95818922670222859038749603875122468409607328327368310045206979952909632056386	110	UVM_INFO @ 390849864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	78513544787334740265426050840941772465671102987179238847929823162296704835957	110	UVM_INFO @ 650981058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	16649306331676672880362949804344995603381944835213919002978688901533968957024	100	UVM_INFO @ 373913383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	43375403470743361449982497732831085303505015241569006761284939732549974338479	100	UVM_INFO @ 262552002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	26792910840804509159379911102797451460607461783804567510909305338190887007615	100	UVM_INFO @ 29694274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	86569555408192601175871267540141423519105704040190110949544393954043735456215	100	UVM_INFO @ 152588847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	5375023298155330093716084377288811626910656557458530471718098721874658910882	100	UVM_INFO @ 124967049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15299521075574916688774137089902777659830348555787491848670080038280960660568	100	UVM_INFO @ 166604095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	69758085314156258763738286911214789183051733442132118846523203950158234131057	100	UVM_INFO @ 28917463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	81501715170336094622314060353722439469884087873484327900480792583492168104766	100	UVM_INFO @ 482064883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	77213267783614368908912251049224354849841207690234443374408377634938624404365	100	UVM_INFO @ 159071145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	99564777156018879259720522562528068524392949419809673144801356200422478801524	100	UVM_INFO @ 199997957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	86559456689393531985000156303946527621701705067762052627426085488045400073362	100	UVM_INFO @ 105651939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				13 test runs
	csrng_regwen	29819001090401872067261054139136056056858501943252049210452757162767530342704	99	UVM_INFO @ 3190585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	6491401727610065196079840546054604019669669064587836553891258356068268769724	99	UVM_INFO @ 2847073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	50091708778512147272664166466376284305404634232510061980885289436367132612813	99	UVM_INFO @ 12339194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	19891966144234670905957298739435338991941709156663460838899015462407795615454	99	UVM_INFO @ 3009126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	94839427040963741913449323769354490215032634302917651643695235564945086896969	99	UVM_INFO @ 5200102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	43189316479417794467045043992365260588937239490100532955427295484850112711829	99	UVM_INFO @ 5212585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	13439626238605714182863325032782504122151887579710684522599612408725358816414	99	UVM_INFO @ 22843012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	98251512211015463236806571660982335187723870552796668330780197383628314222194	99	UVM_INFO @ 3009957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	45386109500800248021300108907203897950788866770232338501852665379291143773896	99	UVM_INFO @ 6099106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	13083424319753796644527480350733737769940811072513857129685810952437878791937	99	UVM_INFO @ 2768797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	69942094143412015159986173409376727510897822499039970561084654168255536588667	99	UVM_INFO @ 5293895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	29878542633285205063773230819049130619431674586368698241603820890459850490197	99	UVM_INFO @ 12708161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	88807950446542407498015297447338955417203325518417800374325178950373429945885	99	UVM_INFO @ 5444583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				8 test runs
	csrng_stress_all_with_rand_reset	49920127074700539254548117727355154588854644804056298788491666938513431684992	None
	csrng_stress_all_with_rand_reset	113151770756557252580782889895758918204397590181126575472411019373597878113817	None
	csrng_stress_all_with_rand_reset	91485013847675262478799041492724922047053105028726575207756645250628682255805	None
	csrng_stress_all_with_rand_reset	26486306374427991592045081089744988610523990719709017358157692251087865408131	None
	csrng_stress_all_with_rand_reset	82974091907508535877415034689823422827393063576594363430343422656474415214870	None
	csrng_stress_all_with_rand_reset	3467133912681706115574956456744853018109058323327858451654999501399380664949	None
	csrng_stress_all_with_rand_reset	58602893972917469411179653424800265895450495465079867168289885293454761074670	None
	csrng_stress_all_with_rand_reset	17522849549199004497290393495445562741607658340703889807042458620319049058152	None
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				3 test runs
	csrng_stress_all_with_rand_reset	91395050021894527908136714323691721418647267184736454099565887984922791815700	125	UVM_INFO @ 1431501375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	105090860047836352969757808989612337869547514616770769023590379731852562349381	119	UVM_INFO @ 5684758482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	67659491242379042561056417312642575166892337327961870771661296898757949803007	122	UVM_INFO @ 208833493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [csrng_common_vseq] wait timeout occurred!				2 test runs
	csrng_csr_mem_rw_with_rand_reset	82337049233009058786399368902628870148585139240964376464159244366200869635323	106	UVM_INFO @ 10015054736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_tl_intg_err	86028167753768362594548050856279193637217910527264939223001144821990042167436	230	UVM_INFO @ 13167267007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])				2 test runs
	csrng_cmds	11107998384236046421545974834049115063687150974133680229128580854913973566419	119	UVM_INFO @ 94282404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	2668855416536317814041212007990663583791789971287549536249426763045062225269	109	UVM_INFO @ 79124554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				1 test run
	csrng_cmds	4823925459259640841790090421579957091014906509721606142780587094453550823123	103	UVM_INFO @ 216425447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				1 test run
	csrng_stress_all_with_rand_reset	10759997260240609925516605525925937497599404209120667187509287950298469909602	118	UVM_INFO @ 901316461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				1 test run
	csrng_regwen	98443218322263578940043791418676170675409123865476541413638914946116858222317	99	UVM_INFO @ 3576322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly				1 test run
	csrng_cmds	5049218610813140827162713311197612865292349281489401815193451201087431688132	108	UVM_INFO @ 17002854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---