Simulation Results: dma

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.86 %
  • code
  • 90.76 %
  • assert
  • 96.61 %
  • func
  • 76.22 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 8.000s 378.635us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 10.000s 1117.787us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 9.000s 1332.589us 50 50 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 31.063us 1 1 100.00
csr_rw 5 5 100.00
dma_csr_rw 2.000s 30.491us 5 5 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 1640.087us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 321.731us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 77.711us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
dma_csr_rw 2.000s 30.491us 5 5 100.00
dma_csr_aliasing 3.000s 321.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 50.000s 2682.527us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 366.000s 33757.303us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 319.000s 21730.315us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 319.000s 21730.315us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 366.000s 33757.303us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1662.000s 539313.215us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 319.000s 21730.315us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 13.000s 1448.457us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 134.000s 16472.079us 3 3 100.00
alert_test 10 10 100.00
dma_alert_test 2.000s 72.995us 10 10 100.00
intr_test 10 10 100.00
dma_intr_test 2.000s 26.205us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
dma_tl_errors 4.000s 526.854us 25 25 100.00
tl_d_illegal_access 25 25 100.00
dma_tl_errors 4.000s 526.854us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
dma_csr_hw_reset 1.000s 31.063us 1 1 100.00
dma_csr_rw 2.000s 30.491us 5 5 100.00
dma_csr_aliasing 3.000s 321.731us 1 1 100.00
dma_same_csr_outstanding 4.000s 922.872us 5 5 100.00
tl_d_partial_access 12 12 100.00
dma_csr_hw_reset 1.000s 31.063us 1 1 100.00
dma_csr_rw 2.000s 30.491us 5 5 100.00
dma_csr_aliasing 3.000s 321.731us 1 1 100.00
dma_same_csr_outstanding 4.000s 922.872us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 29.000s 486.440us 5 5 100.00
dma_generic_stress 1662.000s 539313.215us 5 5 100.00
dma_handshake_stress 319.000s 21730.315us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 11.000s 647.072us 15 15 100.00
tl_intg_err 30 30 100.00
dma_tl_intg_err 5.000s 216.217us 25 25 100.00
dma_sec_cm 2.000s 38.947us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 205.000s 18533.413us 25 25 100.00
dma_longer_transfer 162.000s 35575.516us 5 5 100.00
dma_stress_all_with_rand_reset 12.000s 491.894us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 60848960082014916440446701046668681328327328965503848001828199805146120331598 104
UVM_INFO @ 491894356ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---