Simulation Results

Simulation Results: edn/edn0

19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
83.84 %

code
95.22 %

assert
97.57 %

func
58.74 %

block
96.91 %

line
98.63 %

branch
93.13 %

toggle
89.13 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		98.52%
V2S		100.00%
V3		100.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	edn_smoke	2.000s	50.466us	10	10	100.00
csr_hw_reset				1	1	100.00
	edn_csr_hw_reset	1.000s	22.687us	1	1	100.00
csr_rw				5	5	100.00
	edn_csr_rw	2.000s	47.443us	5	5	100.00
csr_bit_bash				1	1	100.00
	edn_csr_bit_bash	5.000s	143.723us	1	1	100.00
csr_aliasing				1	1	100.00
	edn_csr_aliasing	2.000s	49.284us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	edn_csr_mem_rw_with_rand_reset	2.000s	21.005us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	edn_csr_rw	2.000s	47.443us	5	5	100.00
	edn_csr_aliasing	2.000s	49.284us	1	1	100.00

598/607 passed

98.52 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				100	100	100.00
	edn_genbits	60.000s	4471.831us	100	100	100.00
csrng_commands				100	100	100.00
	edn_genbits	60.000s	4471.831us	100	100	100.00
genbits				100	100	100.00
	edn_genbits	60.000s	4471.831us	100	100	100.00
interrupts				20	20	100.00
	edn_intr	2.000s	39.807us	20	20	100.00
alerts				200	200	100.00
	edn_alert	3.000s	65.678us	200	200	100.00
errs				100	100	100.00
	edn_err	3.000s	65.793us	100	100	100.00
disable				91	100	91.00
	edn_disable	2.000s	39.175us	50	50	100.00
	edn_disable_auto_req_mode	6.000s	500.000us	41	50	82.00
stress_all				30	30	100.00
	edn_stress_all	8.000s	447.844us	30	30	100.00
intr_test				10	10	100.00
	edn_intr_test	2.000s	14.424us	10	10	100.00
alert_test				10	10	100.00
	edn_alert_test	2.000s	33.294us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	edn_tl_errors	6.000s	141.743us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	edn_tl_errors	6.000s	141.743us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	edn_csr_hw_reset	1.000s	22.687us	1	1	100.00
	edn_csr_rw	2.000s	47.443us	5	5	100.00
	edn_csr_aliasing	2.000s	49.284us	1	1	100.00
	edn_same_csr_outstanding	2.000s	42.474us	5	5	100.00
tl_d_partial_access				12	12	100.00
	edn_csr_hw_reset	1.000s	22.687us	1	1	100.00
	edn_csr_rw	2.000s	47.443us	5	5	100.00
	edn_csr_aliasing	2.000s	49.284us	1	1	100.00
	edn_same_csr_outstanding	2.000s	42.474us	5	5	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	edn_sec_cm	11.000s	1149.024us	5	5	100.00
	edn_tl_intg_err	4.000s	126.365us	25	25	100.00
sec_cm_config_regwen				5	5	100.00
	edn_regwen	2.000s	209.808us	5	5	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	3.000s	65.678us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	11.000s	1149.024us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	11.000s	1149.024us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	11.000s	1149.024us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	11.000s	1149.024us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	3.000s	65.678us	200	200	100.00
	edn_sec_cm	11.000s	1149.024us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	3.000s	65.678us	200	200	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	edn_tl_intg_err	4.000s	126.365us	25	25	100.00

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				30	30	100.00
	edn_stress_all_with_rand_reset	105.000s	5139.709us	30	30	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				7 test runs
	edn_disable_auto_req_mode	91440474743126803496971198001954785249463535242467362771694230635096024288463	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	22619227207028110447669292354889736206381384954983987849969948404167107288704	103	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	36427858493015056499462073439744948402953858104345934356204159840975778311133	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	74220871938664515058446567937833825223850887161826658224501930711778646714455	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	14256067942549344160760860017782769235916738872029978441579822771966263169701	103	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	63256332383408317803345651961117386191993202799454128871223150346893218492900	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	89611770164566985072267640653849914047107003183459414908681902289163686158326	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.				2 test runs
	edn_disable_auto_req_mode	65769451234628195166946286961208024380954970697410818334883636744155015323552	103	UVM_INFO @ 38060280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	19014244310789009369425167835336266081447534590421127322708766317925852903085	103	UVM_INFO @ 39202523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---