Simulation Results: edn/edn1

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.75 %
  • code
  • 96.33 %
  • assert
  • 98.70 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.69 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
98.35%
V2S
100.00%
V3
73.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.210s 29.595us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 15.909us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.250s 53.047us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.470s 184.094us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.550s 35.955us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.470s 57.028us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.250s 53.047us 5 5 100.00
edn_csr_aliasing 1.550s 35.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.010s 757.234us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.010s 757.234us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.010s 757.234us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.300s 23.132us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.810s 289.076us 200 200 100.00
errs 100 100 100.00
edn_err 1.660s 28.240us 100 100 100.00
disable 90 100 90.00
edn_disable 1.830s 500.000us 49 50 98.00
edn_disable_auto_req_mode 7.370s 500.000us 41 50 82.00
stress_all 30 30 100.00
edn_stress_all 7.020s 547.461us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.230s 17.576us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.140s 166.391us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.830s 132.276us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.830s 132.276us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.000s 15.909us 1 1 100.00
edn_csr_rw 1.250s 53.047us 5 5 100.00
edn_csr_aliasing 1.550s 35.955us 1 1 100.00
edn_same_csr_outstanding 1.320s 62.668us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.000s 15.909us 1 1 100.00
edn_csr_rw 1.250s 53.047us 5 5 100.00
edn_csr_aliasing 1.550s 35.955us 1 1 100.00
edn_same_csr_outstanding 1.320s 62.668us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.300s 675.036us 5 5 100.00
edn_tl_intg_err 2.820s 184.878us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.160s 57.533us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.810s 289.076us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.300s 675.036us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.300s 675.036us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.300s 675.036us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.300s 675.036us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.810s 289.076us 200 200 100.00
edn_sec_cm 4.300s 675.036us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.810s 289.076us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.820s 184.878us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 22 30 73.33
edn_stress_all_with_rand_reset 84.630s 55784.081us 22 30 73.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 8 test runs
edn_disable_auto_req_mode 17190620019011718456801001222669894571988119353133691658269558842716935695087 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 51677809161581917148137999994916909892902474526714258005880073507601579636536 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 82121016359192206929076874305054846305743231195443829406051210744943500188462 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable 54392131679865169257827590485995791008791325850213886713948381595992348297980 85
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 34438411419670161719448803213875803755301993488905552714419282738979256781535 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 75004768710643300280374682353407160887074828598298082292625915363308098368576 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 90895794854158821351147753641117698817739565416394851844426832783787613173881 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 69939616713876591927402454651679101460439463745095708948649206085483064445383 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 13235175666044868644002212209523180212094634799396961083487140066914628536212 168
UVM_INFO @ 1149165384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 101242775771377461196201336349305925002763645751274542226053855520131844394819 172
UVM_INFO @ 1527618080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 21652009483728660808600704594058347973386843658374996417173853359133237854168 167
UVM_INFO @ 156137259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 5253920256247194047322842774367260357875029146408000520813776750166707360880 157
UVM_INFO @ 726143853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 41795460547147233466675976589082039431510404016643103152636008898742178285696 158
UVM_INFO @ 683805931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 63936501054167866902020010707188744639820590019819669662841110625356479670387 88
UVM_INFO @ 41552746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 39793307098694992437455485298460966669823701006921798602092443096600254432016 88
UVM_INFO @ 14036608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 2 test runs
edn_stress_all_with_rand_reset 5243369145001849695739187210305120226032033441059356567614721293080042838949 141
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 92650541 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
edn_stress_all_with_rand_reset 3918527828086817018871787169726915556768060160722490865314425018699216713688 191
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2127322664 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
UVM_ERROR (cip_base_vseq.sv:1199) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
edn_stress_all_with_rand_reset 104630503519066734997917913731618054844481146463067558122490364199395547829070 294
UVM_INFO @ 1299717382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---