| V1 |
|
100.00% |
| V2 |
|
93.63% |
| V2S |
|
93.33% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 40 | 40 | 100.00 | |||
| gpio_smoke | 2.080s | 1145.038us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.880s | 301.777us | 10 | 10 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.960s | 154.174us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 2.440s | 111.878us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.990s | 12.464us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| gpio_csr_rw | 1.140s | 16.633us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 8.050s | 1526.317us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 3.230s | 195.386us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.930s | 27.956us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| gpio_csr_rw | 1.140s | 16.633us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 3.230s | 195.386us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 20 | 20 | 100.00 | |||
| gpio_random_dout_din | 1.920s | 141.365us | 10 | 10 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.980s | 138.661us | 10 | 10 | 100.00 | |
| out_in_regs_read_write | 10 | 10 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.400s | 103.107us | 10 | 10 | 100.00 | |
| gpio_interrupt_programming | 10 | 10 | 100.00 | |||
| gpio_intr_rand_pgm | 2.160s | 401.068us | 10 | 10 | 100.00 | |
| random_interrupt_trigger | 10 | 10 | 100.00 | |||
| gpio_rand_intr_trigger | 3.720s | 161.564us | 10 | 10 | 100.00 | |
| interrupt_and_noise_filter | 10 | 10 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 2.990s | 766.334us | 10 | 10 | 100.00 | |
| noise_filter_stress | 10 | 10 | 100.00 | |||
| gpio_filter_stress | 22.040s | 1729.250us | 10 | 10 | 100.00 | |
| regs_long_reads_and_writes | 10 | 10 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 7.110s | 655.192us | 10 | 10 | 100.00 | |
| full_random | 10 | 10 | 100.00 | |||
| gpio_full_random | 1.320s | 108.978us | 10 | 10 | 100.00 | |
| stress_all | 1 | 10 | 10.00 | |||
| gpio_stress_all | 81.450s | 30023.656us | 1 | 10 | 10.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| gpio_alert_test | 0.900s | 25.596us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| gpio_intr_test | 0.940s | 204.258us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 3.750s | 3276.919us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 3.750s | 3276.919us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 11 | 12 | 91.67 | |||
| gpio_csr_rw | 1.140s | 16.633us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.770s | 286.527us | 4 | 5 | 80.00 | |
| gpio_csr_aliasing | 3.230s | 195.386us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.990s | 12.464us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 11 | 12 | 91.67 | |||
| gpio_csr_rw | 1.140s | 16.633us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.770s | 286.527us | 4 | 5 | 80.00 | |
| gpio_csr_aliasing | 3.230s | 195.386us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.990s | 12.464us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 28 | 30 | 93.33 | |||
| gpio_tl_intg_err | 3.200s | 207.199us | 23 | 25 | 92.00 | |
| gpio_sec_cm | 1.220s | 229.814us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 23 | 25 | 92.00 | |||
| gpio_tl_intg_err | 3.200s | 207.199us | 23 | 25 | 92.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 10 | 10 | 100.00 | |||
| gpio_rand_straps | 0.890s | 12.133us | 10 | 10 | 100.00 | |
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 11.620s | 2304.999us | 0 | 10 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 50 | 50 | 100.00 | |||
| gpio_inp_prd_cnt | 0.940s | 13.395us | 50 | 50 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| gpio_stress_all | 8729157788385860653000828715529422644432765608854078459569624474033267658673 | 75 |
UVM_INFO @ 32554825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 89210995645623967624609506801205769621031527475088199183678822503196122935576 | 1964 |
UVM_INFO @ 24626932945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 9625020617245378931341535655567619691832017551704543464459122294985152000033 | 122 |
UVM_INFO @ 2471056413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 109976592991143622179718490091504941815041205836826856419425115075352239351672 | 1144 |
UVM_INFO @ 3660013321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 12575629200966683895997729844190359308548467122922215826352469656543281118532 | 1396 |
UVM_INFO @ 30023656217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 111147094708585388456701697052178095180479910832135053395766159384278533558490 | 717 |
UVM_INFO @ 2763312135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 17791062169524754845006441450989385591228480238258197933072604709909384556455 | 1186 |
UVM_INFO @ 9941696687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 71314993094918754534824402516370365417025263115885353234756446380284196788720 | 321 |
UVM_INFO @ 1192877133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 36781232138290876947022796550421948460527224318164504688017708901785029025602 | 76 |
UVM_INFO @ 685843180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 5 test runs | |||
| gpio_stress_all_with_rand_reset | 6327140972087725146403074001208640486149941625649507400056781337184014296253 | 78 |
UVM_INFO @ 4239886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 56647666908765899508863796041481685740845795155828860321528214121540275254872 | 78 |
UVM_INFO @ 2558343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 111247161938158099675060339707433197938549225908939025874518781243556016761186 | 78 |
UVM_INFO @ 15258669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 103766218221309830302037861585090733381174089519415351437079911378395613133462 | 80 |
UVM_INFO @ 4589801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 91971181354790803144355896677792637903565042709058241378119747751400561720488 | 78 |
UVM_INFO @ 25756526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) | 5 test runs | |||
| gpio_stress_all_with_rand_reset | 4064672901093599389757718365996768300303724408908515715687910233964804435768 | 80 |
UVM_INFO @ 7887396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 50588542537410979058555966754055116248612139578758200629312181852721503435643 | 81 |
UVM_INFO @ 893743781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 7277929369851906393021418169420038320479712069986408685275735677333934522315 | 80 |
UVM_INFO @ 35987628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 113491381299631180598600941125382322140580015677786198616637114624516826356159 | 235 |
UVM_INFO @ 2304998891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 78439147813726652557350679521496063078100880552461158726669694236205273377867 | 243 |
UVM_INFO @ 1725788943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 1 test run | |||
| gpio_same_csr_outstanding | 10469996277802408661955553083063477233811800814503698966836451939838948974187 | 79 |
UVM_INFO @ 93997447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: * | 1 test run | |||
| gpio_tl_intg_err | 42821836300090154656837449377242494353573493114423391810194337966299041620745 | 136 |
UVM_INFO @ 67194677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_*.value_* reset value: * | 1 test run | |||
| gpio_tl_intg_err | 35660709574607321328162978731306718291775223441247672205669611089230456645147 | 134 |
UVM_INFO @ 48372067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|