Simulation Results: hmac

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.69 %
  • code
  • 96.11 %
  • assert
  • 96.96 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 24.000s 401.170us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 20.555us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 71.601us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 2271.885us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.000s 498.724us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 588.000s 284123.282us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 71.601us 5 5 100.00
hmac_csr_aliasing 7.000s 498.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 120.000s 27944.683us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 97.000s 2272.098us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 342.000s 11153.162us 30 30 100.00
hmac_test_sha384_vectors 761.000s 87193.233us 75 75 100.00
hmac_test_sha512_vectors 670.000s 82811.059us 75 75 100.00
hmac_test_hmac256_vectors 28.000s 1955.838us 50 50 100.00
hmac_test_hmac384_vectors 21.000s 481.108us 60 60 100.00
hmac_test_hmac512_vectors 26.000s 542.008us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 58.000s 24814.926us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 437.000s 136449.211us 10 10 100.00
error 10 10 100.00
hmac_error 132.000s 3114.312us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 140.000s 85176.076us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 24.000s 401.170us 10 10 100.00
hmac_long_msg 120.000s 27944.683us 10 10 100.00
hmac_back_pressure 97.000s 2272.098us 25 25 100.00
hmac_datapath_stress 437.000s 136449.211us 10 10 100.00
hmac_burst_wr 58.000s 24814.926us 50 50 100.00
hmac_stress_all 1033.000s 91378.966us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 24.000s 401.170us 10 10 100.00
hmac_long_msg 120.000s 27944.683us 10 10 100.00
hmac_back_pressure 97.000s 2272.098us 25 25 100.00
hmac_datapath_stress 437.000s 136449.211us 10 10 100.00
hmac_wipe_secret 140.000s 85176.076us 10 10 100.00
hmac_test_sha256_vectors 342.000s 11153.162us 30 30 100.00
hmac_test_sha384_vectors 761.000s 87193.233us 75 75 100.00
hmac_test_sha512_vectors 670.000s 82811.059us 75 75 100.00
hmac_test_hmac256_vectors 28.000s 1955.838us 50 50 100.00
hmac_test_hmac384_vectors 21.000s 481.108us 60 60 100.00
hmac_test_hmac512_vectors 26.000s 542.008us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 24.000s 401.170us 10 10 100.00
hmac_long_msg 120.000s 27944.683us 10 10 100.00
hmac_back_pressure 97.000s 2272.098us 25 25 100.00
hmac_datapath_stress 437.000s 136449.211us 10 10 100.00
hmac_burst_wr 58.000s 24814.926us 50 50 100.00
hmac_error 132.000s 3114.312us 10 10 100.00
hmac_wipe_secret 140.000s 85176.076us 10 10 100.00
hmac_test_sha256_vectors 342.000s 11153.162us 30 30 100.00
hmac_test_sha384_vectors 761.000s 87193.233us 75 75 100.00
hmac_test_sha512_vectors 670.000s 82811.059us 75 75 100.00
hmac_test_hmac256_vectors 28.000s 1955.838us 50 50 100.00
hmac_test_hmac384_vectors 21.000s 481.108us 60 60 100.00
hmac_test_hmac512_vectors 26.000s 542.008us 75 75 100.00
hmac_stress_all 1033.000s 91378.966us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1033.000s 91378.966us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 11.537us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 13.583us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 14.000s 159.543us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 14.000s 159.543us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 20.555us 1 1 100.00
hmac_csr_rw 2.000s 71.601us 5 5 100.00
hmac_csr_aliasing 7.000s 498.724us 1 1 100.00
hmac_same_csr_outstanding 4.000s 189.832us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 20.555us 1 1 100.00
hmac_csr_rw 2.000s 71.601us 5 5 100.00
hmac_csr_aliasing 7.000s 498.724us 1 1 100.00
hmac_same_csr_outstanding 4.000s 189.832us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 66.049us 5 5 100.00
hmac_tl_intg_err 10.000s 226.070us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 10.000s 226.070us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 24.000s 401.170us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 13.000s 250.440us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 287.000s 25879.928us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 723.723us 1 1 100.00