Simulation Results: keymgr_dpe

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 66.36 %
  • code
  • 83.91 %
  • assert
  • 97.14 %
  • func
  • 18.04 %
  • block
  • 98.09 %
  • line
  • 98.74 %
  • branch
  • 93.62 %
  • toggle
  • 61.74 %
  • FSM
  • 81.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
keymgr_dpe_smoke 39.000s 2468.986us 10 10 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 2.000s 25.504us 1 1 100.00
csr_rw 5 5 100.00
keymgr_dpe_csr_rw 2.000s 15.965us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 19.000s 4220.006us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 3.000s 171.561us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 31.532us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_dpe_csr_rw 2.000s 15.965us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 171.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
keymgr_dpe_intr_test 2.000s 21.600us 10 10 100.00
alert_test 10 10 100.00
keymgr_dpe_alert_test 2.000s 32.337us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 591.596us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 591.596us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 25.504us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 15.965us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 171.561us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 108.934us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 25.504us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 15.965us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 171.561us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 108.934us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
keymgr_dpe_sec_cm 17.000s 4913.355us 5 5 100.00
keymgr_dpe_tl_intg_err 7.000s 288.438us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 128.125us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 128.125us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 128.125us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 128.125us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 9.000s 523.548us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 17.000s 4913.355us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 17.000s 4913.355us 5 5 100.00