Simulation Results: lc_ctrl/volatile_unlock_disabled

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.23 %
  • code
  • 93.18 %
  • assert
  • 96.69 %
  • func
  • 89.81 %
  • block
  • 96.70 %
  • line
  • 97.39 %
  • branch
  • 91.61 %
  • toggle
  • 88.48 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.53%
V2S
99.33%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.000s 143.190us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 25.000s 26.643us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 19.000s 18.995us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 28.000s 2089.402us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 26.000s 47.071us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 24.000s 94.586us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 19.000s 18.995us 5 5 100.00
lc_ctrl_csr_aliasing 26.000s 47.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 256.119us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.000s 797.150us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 25.000s 36.776us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 5.000s 1215.025us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 24.000s 375.474us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_ctrl_prog_failure 5.000s 1215.025us 20 20 100.00
lc_ctrl_errors 24.000s 375.474us 20 20 100.00
lc_ctrl_security_escalation 10.000s 859.776us 20 20 100.00
lc_ctrl_jtag_state_failure 52.000s 24299.501us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.000s 2116.890us 19 20 95.00
lc_ctrl_jtag_errors 44.000s 2475.345us 20 20 100.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 8.000s 3973.114us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.000s 769.161us 19 20 95.00
lc_ctrl_jtag_prog_failure 13.000s 2116.890us 19 20 95.00
lc_ctrl_jtag_errors 44.000s 2475.345us 20 20 100.00
lc_ctrl_jtag_access 26.000s 1481.014us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 20.000s 808.651us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 6.000s 234.499us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 47.437us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 25.000s 1649.343us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 17.000s 1675.719us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 53.129us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.000s 1170.959us 10 10 100.00
lc_ctrl_jtag_alert_test 14.000s 102.164us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 13.000s 2849.236us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 25.160us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 159.000s 19212.915us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 26.000s 130.354us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 439.182us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 439.182us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 25.000s 26.643us 1 1 100.00
lc_ctrl_csr_rw 19.000s 18.995us 5 5 100.00
lc_ctrl_csr_aliasing 26.000s 47.071us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 97.325us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 25.000s 26.643us 1 1 100.00
lc_ctrl_csr_rw 19.000s 18.995us 5 5 100.00
lc_ctrl_csr_aliasing 26.000s 47.071us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 97.325us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 6.000s 1041.375us 5 5 100.00
lc_ctrl_tl_intg_err 5.000s 233.970us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 5.000s 233.970us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.000s 797.150us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_ctrl_sec_cm 6.000s 1041.375us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_ctrl_sec_cm 6.000s 1041.375us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_ctrl_sec_cm 6.000s 1041.375us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_ctrl_sec_cm 6.000s 1041.375us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_ctrl_sec_cm 6.000s 1041.375us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_ctrl_sec_cm 6.000s 1041.375us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_ctrl_sec_cm 6.000s 1041.375us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 10.000s 877.264us 20 20 100.00
lc_ctrl_sec_cm 6.000s 1041.375us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 10.000s 859.776us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 4.000s 256.119us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.000s 769.161us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 1607.002us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 1607.002us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 12.000s 846.943us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.000s 2830.791us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.000s 2830.791us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 91.000s 34131.430us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 101293502311356447906193797324416735395174208273283150908946482673464170008021 1365
UVM_INFO @ 6687114649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30690478086945530532199163339980455039157489356575316651326248491694517343436 323
UVM_INFO @ 497837568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42925802439189383689142332790262570369993604404013600537837091917184981898371 709
UVM_INFO @ 2137009890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32459308067543701015696054589636113617406286298163102002557759381104351684505 2829
UVM_INFO @ 2652680373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 39675986038980868975780132064503874576131564381343723393323543287717414181969 2193
UVM_INFO @ 34131429616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_post_trans 60247444378000655597699950279713474622512852858134973932583332005824112325214 180
UVM_INFO @ 79953196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 70433412812627941847809343907451690291123786536606787380703015448765959777 178
UVM_INFO @ 53566256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---