Simulation Results: lc_ctrl/volatile_unlock_enabled

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.61 %
  • code
  • 94.19 %
  • assert
  • 96.83 %
  • func
  • 89.81 %
  • block
  • 97.20 %
  • line
  • 97.72 %
  • branch
  • 92.91 %
  • toggle
  • 88.51 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.30%
V2S
100.00%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.000s 315.011us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.839us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 14.083us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 75.422us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 41.533us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 27.010us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 14.083us 5 5 100.00
lc_ctrl_csr_aliasing 3.000s 41.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 100.364us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1457.562us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 3.000s 41.683us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 6.000s 673.690us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 12.000s 1485.596us 20 20 100.00
security_escalation 137 140 97.86
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_ctrl_prog_failure 6.000s 673.690us 20 20 100.00
lc_ctrl_errors 12.000s 1485.596us 20 20 100.00
lc_ctrl_security_escalation 12.000s 901.525us 20 20 100.00
lc_ctrl_jtag_state_failure 86.000s 10157.216us 19 20 95.00
lc_ctrl_jtag_prog_failure 17.000s 783.432us 19 20 95.00
lc_ctrl_jtag_errors 77.000s 21037.142us 19 20 95.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 14.000s 798.998us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.000s 13912.320us 20 20 100.00
lc_ctrl_jtag_prog_failure 17.000s 783.432us 19 20 95.00
lc_ctrl_jtag_errors 77.000s 21037.142us 19 20 95.00
lc_ctrl_jtag_access 15.000s 589.195us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 27.000s 1533.921us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 60.047us 10 10 100.00
lc_ctrl_jtag_csr_rw 5.000s 533.427us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 21.000s 2394.994us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 31.000s 1555.860us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 4.000s 156.835us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.000s 128.130us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 26.395us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 14.000s 2405.776us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.757us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 207.000s 61567.709us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 3.000s 22.455us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 110.484us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 110.484us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 17.839us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.083us 5 5 100.00
lc_ctrl_csr_aliasing 3.000s 41.533us 1 1 100.00
lc_ctrl_same_csr_outstanding 4.000s 47.172us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 17.839us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.083us 5 5 100.00
lc_ctrl_csr_aliasing 3.000s 41.533us 1 1 100.00
lc_ctrl_same_csr_outstanding 4.000s 47.172us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 5.000s 258.517us 5 5 100.00
lc_ctrl_tl_intg_err 5.000s 123.324us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 5.000s 123.324us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1457.562us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_ctrl_sec_cm 5.000s 258.517us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_ctrl_sec_cm 5.000s 258.517us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_ctrl_sec_cm 5.000s 258.517us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_ctrl_sec_cm 5.000s 258.517us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_ctrl_sec_cm 5.000s 258.517us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_ctrl_sec_cm 5.000s 258.517us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_ctrl_sec_cm 5.000s 258.517us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 8.000s 1428.234us 20 20 100.00
lc_ctrl_sec_cm 5.000s 258.517us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 12.000s 901.525us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 4.000s 100.364us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.000s 13912.320us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 4615.419us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 4615.419us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 13.000s 539.902us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.000s 859.075us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.000s 859.075us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
lc_ctrl_stress_all_with_rand_reset 48.000s 2805.304us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 13388254711139341372688756937508494910555853847951459144018258403136832240812 165
UVM_INFO @ 1870256333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 110266113799405369441463706363971526350982495252241574587615304164735048610496 2764
UVM_INFO @ 2805303565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96726715347541097792242646735698002998394813134021586334508548646794318188976 2808
UVM_INFO @ 1898361633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14899412693825077993289730680207227799630088038449425817518048572926698702238 552
UVM_INFO @ 1649346210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 56979328104783378970259689344215607975895107949503679828145337416902370851301 4755
UVM_INFO @ 5182850082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 2 test runs
lc_ctrl_stress_all_with_rand_reset 81211932822414341731069612718155074824407147685029664517446249616923216548712 5750
UVM_INFO @ 12911949276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51586811628959508873847475351896774373201027459119921903707905528695639777717 3344
UVM_INFO @ 1140051500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 19904181533737672004211315663442543858278422875749311900825288625904084634740 177
UVM_INFO @ 69208389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 103520376781618668196728701946875662930489871382397221117965022655920950624959 177
UVM_INFO @ 533352691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 111264465845810160568954643918218035759757831177999731609417714252531240240492 1266
UVM_INFO @ 3275639522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---