Simulation Results: otbn

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.92 %
  • code
  • 95.73 %
  • assert
  • 98.01 %
  • func
  • 100.00 %
  • block
  • 99.47 %
  • line
  • 99.61 %
  • branch
  • 93.25 %
  • toggle
  • 90.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.93%
V2S
96.05%
V3
50.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 39.163us 1 1 100.00
single_binary 100 100 100.00
otbn_single 156.000s 616.369us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 9.000s 103.546us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 9.000s 42.545us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 14.000s 2262.128us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 9.000s 15.078us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 42.641us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 9.000s 42.545us 5 5 100.00
otbn_csr_aliasing 9.000s 15.078us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 86.000s 13411.894us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 35.000s 1450.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 53.000s 146.305us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 56.000s 1007.036us 1 1 100.00
back_to_back 8 10 80.00
otbn_multi 3602.078s 0.000us 8 10 80.00
stress_all 10 10 100.00
otbn_stress_all 132.000s 1457.833us 10 10 100.00
lc_escalation 57 60 95.00
otbn_escalate 23.000s 553.560us 57 60 95.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 9.000s 32.287us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 16.000s 96.823us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 10.000s 21.204us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 8.000s 45.773us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 9.000s 498.463us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 9.000s 498.463us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 9.000s 103.546us 1 1 100.00
otbn_csr_rw 9.000s 42.545us 5 5 100.00
otbn_csr_aliasing 9.000s 15.078us 1 1 100.00
otbn_same_csr_outstanding 5.000s 28.115us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 9.000s 103.546us 1 1 100.00
otbn_csr_rw 9.000s 42.545us 5 5 100.00
otbn_csr_aliasing 9.000s 15.078us 1 1 100.00
otbn_same_csr_outstanding 5.000s 28.115us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 12.000s 25.555us 10 10 100.00
otbn_dmem_err 16.000s 34.962us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 14.000s 69.968us 4 5 80.00
otbn_controller_ispr_rdata_err 11.000s 118.065us 5 5 100.00
otbn_mac_bignum_acc_err 13.000s 63.993us 5 5 100.00
otbn_urnd_err 6.000s 21.379us 2 2 100.00
illegal_bus_access 4 5 80.00
otbn_illegal_mem_acc 7.000s 17.576us 4 5 80.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 8.000s 21.346us 2 2 100.00
otbn_non_sec_partial_wipe 8 10 80.00
otbn_partial_wipe 7.000s 53.203us 8 10 80.00
tl_intg_err 30 30 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
otbn_tl_intg_err 35.000s 203.058us 25 25 100.00
passthru_mem_tl_intg_err 3 5 60.00
otbn_passthru_mem_tl_intg_err 54.000s 1851.881us 3 5 60.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 39.163us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 16.000s 34.962us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 12.000s 25.555us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 35.000s 203.058us 25 25 100.00
sec_cm_controller_fsm_global_esc 57 60 95.00
otbn_escalate 23.000s 553.560us 57 60 95.00
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 12.000s 25.555us 10 10 100.00
otbn_dmem_err 16.000s 34.962us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 32.287us 5 5 100.00
otbn_illegal_mem_acc 7.000s 17.576us 4 5 80.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 156.000s 616.369us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 12.000s 25.555us 10 10 100.00
otbn_dmem_err 16.000s 34.962us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 32.287us 5 5 100.00
otbn_illegal_mem_acc 7.000s 17.576us 4 5 80.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 57 60 95.00
otbn_escalate 23.000s 553.560us 57 60 95.00
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 12.000s 25.555us 10 10 100.00
otbn_dmem_err 16.000s 34.962us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 32.287us 5 5 100.00
otbn_illegal_mem_acc 7.000s 17.576us 4 5 80.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 156.000s 616.369us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 10.000s 38.360us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 7.000s 43.993us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 70.000s 383.135us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 70.000s 383.135us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 12.000s 62.413us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 8 10 80.00
otbn_rf_bignum_intg_err 14.000s 78.274us 8 10 80.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 15.000s 42.039us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 15.000s 42.039us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 16.000s 125.970us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 156.000s 616.369us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 156.000s 616.369us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 156.000s 616.369us 100 100 100.00
sec_cm_write_mem_integrity 8 10 80.00
otbn_multi 3602.078s 0.000us 8 10 80.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 156.000s 616.369us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 156.000s 616.369us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 15.000s 49.041us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 156.000s 616.369us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 913.000s 4668.733us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 468.000s 6152.625us 5 10 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 58.613us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
otbn_stress_all_with_rand_reset 35274247567416582448307781024250728592047848686525688606116658138277537152784 321
UVM_INFO @ 629325851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 19085853471258227479272094990363351995771303020593682709238162934756794486512 580
UVM_INFO @ 5591953675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 45247589754863566820024938409298494414191162023834833435119830681771482395196 207
UVM_INFO @ 447134802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 83731143725371823880112029279555310436174313515259612763634839443568155291035 295
UVM_INFO @ 1357185330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 3 test runs
otbn_multi 61812635473537348978775737800928354086422731995504781705738508764443286826971 149
UVM_INFO @ 59034701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 69129324910029218580694717408529477288337395182300711746105256191050622547864 91
UVM_INFO @ 33478318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 99472083359299613581858587693763005300084736723636839895347286933689559840151 101
UVM_INFO @ 101936384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 3 test runs
otbn_alu_bignum_mod_err 50947720779623770680663627692098914355664318197803235148097528573856209952937 109
UVM_INFO @ 153047069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 1591227787540748692966738289062365105173766862935695044970920232487014214213 110
UVM_INFO @ 58633741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 87420599335017077373465334982603855259850152977012698474501883043124195996232 115
UVM_INFO @ 49871227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed 2 test runs
otbn_partial_wipe 53229597925862282210868911999139379036939136532420889216937069799556784192105 109
UVM_ERROR @ 7505528 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 7505528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 39774618510288608825142111608508421183611331791201348075193218245240715220187 107
UVM_ERROR @ 4133528 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 4133528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_escalate 26948245423743187040579848185311946184938267646503416499332787365651261877001 117
UVM_ERROR @ 297476441 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 297476441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 94765329276203386611892016860504258311642999285817812107274406188597082569542 113
UVM_ERROR @ 30510303 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 30510303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_illegal_mem_acc 9002672484512305815866443981964186562695874615065725646690848695204703141065 111
UVM_INFO @ 156356878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
otbn_multi 35937325200184003238894001862402116442462562269533745610629464402186770869197 None
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 23481545974877096433265786604045743026029785043488667386535589274595462554672 255
UVM_INFO @ 693552826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 46504040641215709183475016699164369564265858436451245315549372236337799957303 107
UVM_INFO @ 4967249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---