Simulation Results

Simulation Results: rom_ctrl/32kb

19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
96.99 %

code
94.00 %

assert
97.67 %

func
99.29 %

block
96.76 %

line
97.24 %

branch
94.09 %

toggle
84.66 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.77%
V2S		96.61%
V3		80.00%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	5.000s	562.780us	2	2	100.00
csr_hw_reset				1	1	100.00
	rom_ctrl_csr_hw_reset	4.000s	227.567us	1	1	100.00
csr_rw				5	5	100.00
	rom_ctrl_csr_rw	4.000s	371.189us	5	5	100.00
csr_bit_bash				1	1	100.00
	rom_ctrl_csr_bit_bash	3.000s	215.488us	1	1	100.00
csr_aliasing				1	1	100.00
	rom_ctrl_csr_aliasing	4.000s	158.475us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	5.000s	1057.062us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rom_ctrl_csr_rw	4.000s	371.189us	5	5	100.00
	rom_ctrl_csr_aliasing	4.000s	158.475us	1	1	100.00
mem_walk				1	1	100.00
	rom_ctrl_mem_walk	3.000s	251.318us	1	1	100.00
mem_partial_access				1	1	100.00
	rom_ctrl_mem_partial_access	3.000s	134.686us	1	1	100.00

68/71 passed

95.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				0	2	0.00
	rom_ctrl_max_throughput_chk	4.000s	114.512us	0	2	0.00
stress_all				19	20	95.00
	rom_ctrl_stress_all	17.000s	2185.342us	19	20	95.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	7.000s	1130.354us	2	2	100.00
alert_test				10	10	100.00
	rom_ctrl_alert_test	5.000s	124.522us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rom_ctrl_tl_errors	11.000s	2110.218us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rom_ctrl_tl_errors	11.000s	2110.218us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rom_ctrl_csr_hw_reset	4.000s	227.567us	1	1	100.00
	rom_ctrl_csr_rw	4.000s	371.189us	5	5	100.00
	rom_ctrl_csr_aliasing	4.000s	158.475us	1	1	100.00
	rom_ctrl_same_csr_outstanding	5.000s	536.156us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rom_ctrl_csr_hw_reset	4.000s	227.567us	1	1	100.00
	rom_ctrl_csr_rw	4.000s	371.189us	5	5	100.00
	rom_ctrl_csr_aliasing	4.000s	158.475us	1	1	100.00
	rom_ctrl_same_csr_outstanding	5.000s	536.156us	5	5	100.00

V2S

57/59 passed

96.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
passthru_mem_tl_intg_err				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	19.000s	4363.593us	5	5	100.00
tl_intg_err				30	30	100.00
	rom_ctrl_sec_cm	132.000s	917.231us	5	5	100.00
	rom_ctrl_tl_intg_err	37.000s	350.211us	25	25	100.00
prim_fsm_check				5	5	100.00
	rom_ctrl_sec_cm	132.000s	917.231us	5	5	100.00
prim_count_check				5	5	100.00
	rom_ctrl_sec_cm	132.000s	917.231us	5	5	100.00
sec_cm_checker_ctr_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
sec_cm_checker_ctrl_flow_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
sec_cm_checker_fsm_local_esc				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
sec_cm_compare_ctrl_flow_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
sec_cm_compare_ctr_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
sec_cm_compare_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	132.000s	917.231us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	rom_ctrl_sec_cm	132.000s	917.231us	5	5	100.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	5.000s	562.780us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	5.000s	562.780us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	5.000s	562.780us	2	2	100.00
sec_cm_bus_integrity				25	25	100.00
	rom_ctrl_tl_intg_err	37.000s	350.211us	25	25	100.00
sec_cm_bus_local_esc				20	22	90.91
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
	rom_ctrl_kmac_err_chk	7.000s	1130.354us	2	2	100.00
sec_cm_mux_mubi				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
sec_cm_mux_consistency				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
sec_cm_ctrl_redun				18	20	90.00
	rom_ctrl_corrupt_sig_fatal_chk	88.000s	24700.284us	18	20	90.00
sec_cm_ctrl_mem_integrity				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	19.000s	4363.593us	5	5	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	132.000s	917.231us	5	5	100.00

16/20 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				16	20	80.00
	rom_ctrl_stress_all_with_rand_reset	123.000s	6610.998us	16	20	80.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:*				5 test runs
	rom_ctrl_stress_all_with_rand_reset	34389378774313341312408220767559791147820660534707870065682195437512180931017	95	UVM_INFO @ 1189735354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all	51630530614775227614437367560985909390721989533470278998496410374756119898377	87	UVM_INFO @ 88713966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	5759904683579525491294089440033746176669468652884219761700057778381864357070	93	UVM_INFO @ 367444792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	44797022410075743954181895445274431503341702150015231163852740372128080399255	92	UVM_INFO @ 1272168624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	113866161015997505906338753509463972847637252593385624524255408218643273725561	90	UVM_INFO @ 357457744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [] vs [*])				2 test runs
	rom_ctrl_max_throughput_chk	101157119273165538527206384581772490287233293763540761607599696904787036621791	88	UVM_INFO @ 85470493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_max_throughput_chk	26015701759194894297764152784652060533872864475568651017098850322198075297400	88	UVM_INFO @ 114511506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)				2 test runs
	rom_ctrl_corrupt_sig_fatal_chk	91825737210239658394121762518922779625253718483952100180360814715071611679357	91	UVM_INFO @ 1597755601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	32365781958722896721643273491802159081159993999996930978440195925791129849870	96	UVM_INFO @ 1646739870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---