Simulation Results

Simulation Results: rv_dm/use_dmi_interface

19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.85 %

code
83.65 %

assert
96.90 %

func
98.00 %

block
94.12 %

line
94.63 %

branch
84.10 %

toggle
75.51 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		44.44%
V2S		100.00%
V3		15.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	51.000s	2105.824us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	46.000s	1433.517us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	48.000s	516.915us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	44.000s	3329.357us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	47.000s	331.559us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	55.000s	16290.827us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	54.000s	16529.243us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	64.000s	21601.980us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	98.000s	51287.503us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	44.000s	381.504us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	48.000s	446.236us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	38.000s	438.978us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	42.000s	187.413us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	42.000s	608.249us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	38.000s	626.554us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	44.000s	63.255us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	43.000s	937.439us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	44.000s	381.504us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	50.000s	558.471us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	48.000s	742.643us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	38.000s	438.978us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	37.000s	80.359us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	46.000s	465.772us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	52.000s	161.911us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	85.000s	9396.072us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	75.000s	1118.669us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	47.000s	253.400us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	75.000s	1118.669us	1	1	100.00
	rv_dm_csr_rw	52.000s	161.911us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	46.000s	80.853us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	35.000s	45.534us	1	1	100.00

80/180 passed

44.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	51.000s	2105.824us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	43.000s	495.796us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	43.000s	530.403us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	47.000s	151.943us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	46.000s	2754.597us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	61.000s	16804.650us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	47.000s	80.798us	0	20	0.00
bad_sba				2	20	10.00
	rv_dm_bad_sba_tl_access	64.000s	8396.513us	2	20	10.00
sba_autoincrement				3	20	15.00
	rv_dm_autoincr_sba_tl_access	180.000s	167593.618us	3	20	15.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	33.000s	625.703us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	40.000s	1220.730us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	41.000s	940.159us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	44.000s	241.198us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	41.000s	11357.639us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	112.000s	36394.195us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	49.000s	167.685us	1	1	100.00
stress_all				2	20	10.00
	rv_dm_stress_all	10802.269s	0.000us	2	20	10.00
alert_test				10	10	100.00
	rv_dm_alert_test	49.000s	28.423us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	50.000s	967.071us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	50.000s	967.071us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	75.000s	1118.669us	1	1	100.00
	rv_dm_csr_hw_reset	46.000s	465.772us	1	1	100.00
	rv_dm_csr_rw	52.000s	161.911us	5	5	100.00
	rv_dm_same_csr_outstanding	45.000s	183.765us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	75.000s	1118.669us	1	1	100.00
	rv_dm_csr_hw_reset	46.000s	465.772us	1	1	100.00
	rv_dm_csr_rw	52.000s	161.911us	5	5	100.00
	rv_dm_same_csr_outstanding	45.000s	183.765us	5	5	100.00

V2S

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	47.000s	615.096us	5	5	100.00
	rv_dm_tl_intg_err	59.000s	2917.100us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	59.000s	2917.100us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	40.000s	1220.730us	2	2	100.00
	rv_dm_debug_disabled	37.000s	65.331us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	40.000s	1220.730us	2	2	100.00
	rv_dm_debug_disabled	37.000s	65.331us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	51.000s	2105.824us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				10	10	100.00
	rv_dm_buffered_enable	48.000s	112.939us	10	10	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	50.000s	130.624us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	50.000s	130.624us	4	4	100.00
sec_cm_exec_ctrl_mubi				10	10	100.00
	rv_dm_buffered_enable	48.000s	112.939us	10	10	100.00

3/20 passed

15.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				3	20	15.00
	rv_dm_stress_all_with_rand_reset	88.000s	3948.670us	3	20	15.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	609.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				40 test runs
	rv_dm_sba_tl_access	22207255519694262728859852154774726942924335046148624853369108543444826793598	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23811
	rv_dm_sba_tl_access	7023303921372993749277177823201510075261253206963296344235128499319829846389	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23819
	rv_dm_sba_tl_access	47925427283238156374933908958723415358831925420310165032933482377234742901673	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23822
	rv_dm_autoincr_sba_tl_access	10698248148211946865709736692210693714672130288164953022088577892980149367840	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_sba_tl_access	48085380920845078532046452004235765059951139507841039115770532447068079430291	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23856
	rv_dm_bad_sba_tl_access	93260585626500336187750448733104675868667631630518375162120670445921204128492	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24141
	rv_dm_autoincr_sba_tl_access	86193356288230181053945595813333744665328708278772862314571626572515543689311	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23996
	rv_dm_sba_tl_access	91486930065503293377312375654090845819899658413565475554350965058352010040700	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23829
	rv_dm_sba_tl_access	79587741946237341015551865884153663189463111945098909057135931526168965117551	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23819
	rv_dm_delayed_resp_sba_tl_access	28619359129771637772982794201746955237288066502939995988889246653282835257044	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23788
	rv_dm_bad_sba_tl_access	84520989635824327449253373604734443478178470020114733559864194762549264105077	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23819
	rv_dm_sba_tl_access	90832180474488431875072500588798178026904253543839423938054382890478344682068	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23852
	rv_dm_delayed_resp_sba_tl_access	48719533703680305504539455014395532956684310225872767062600209898072571203116	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_bad_sba_tl_access	84515712817451785671194681848252746453245306920107806606912706373990084242096	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23898
	rv_dm_autoincr_sba_tl_access	40491878851301872822492304451662343339275321427681623333749176451567230739407	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23861
	rv_dm_sba_tl_access	89350388633044444083430118318534773870104551322805247192455633679682484259	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_bad_sba_tl_access	62223240497659744734102109652424448699591830903276638491534070766446315062550	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23804
	rv_dm_sba_tl_access	56796706242257355883221532085496527277918619014865312153311754217476480464364	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_bad_sba_tl_access	88273899122803903879180638478764204051549657330895549785811561133129376684839	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23876
	rv_dm_sba_tl_access	88720213511309026593461435346845859910985620331209084693059307871096372684277	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23829
	rv_dm_sba_tl_access	110393616333770212392217206673860309747821198629819871840362944584309507010011	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23729
	rv_dm_bad_sba_tl_access	49765506091408379684973432458484834508329079826385475504558403656055013181823	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23783
	rv_dm_autoincr_sba_tl_access	57203750296895198922655032535588876139396520815858504710127959926040317300452	150	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23905
	rv_dm_sba_tl_access	43394717721565796958936281403206286622841674533950657204229232267617143969382	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23884
	rv_dm_delayed_resp_sba_tl_access	48848776872078782097497437067073777847176988097100910400297185673528751074591	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_autoincr_sba_tl_access	107765991356444783974369251782805176736531640886477868923426834946439926421263	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23772
	rv_dm_sba_tl_access	19099490998186272060024517098298908876654713700029888348661326097234487029737	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23818
	rv_dm_bad_sba_tl_access	43789337290768645205676120416124075886805136182733348931257087885506351116272	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23957
	rv_dm_autoincr_sba_tl_access	31345931965079917068246353587362917882460964453291974883056314188030368555313	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_sba_tl_access	49883868951524422944488109944853278290699918075482599373845444276079841002553	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
	rv_dm_bad_sba_tl_access	5477061931522644022199284581325662891800063288034914182161316873068788257237	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23956
	rv_dm_sba_tl_access	27139429699678970790668711761986505103902104405362248796969344288744739576451	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23890
	rv_dm_sba_tl_access	45142700409914846093532153735177137716714466399046639760380859617396643942202	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_autoincr_sba_tl_access	20508979220474729637190826505456062273217147108839788182113607833303541748168	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23971
	rv_dm_sba_tl_access	100922383495936105163416961116684052923957462192004605122150354525318435418524	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23860
	rv_dm_sba_tl_access	62124697136605657538331952281219992809252094198025191900102610039521702873219	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23806
	rv_dm_bad_sba_tl_access	112066225870328469651214462720522786727036432596166605405896081885605674215350	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23913
	rv_dm_autoincr_sba_tl_access	105047603777331996348330188953410039674576688370078096471579185822247716421003	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10109
	rv_dm_sba_tl_access	7006078374144429542997940809194156990384257882472405201140836165346136073407	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23790
	rv_dm_sba_tl_access	13387647408160696777851146078113711010540824888479950520775622083970095848121	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23821
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				35 test runs
	rv_dm_delayed_resp_sba_tl_access	63265330795042014040606756773211688026735240837180169378115033926121116713196	107	UVM_INFO @ 290531553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	51122831528007023817044313427343056391240839668324410057551579514678218270780	107	UVM_INFO @ 53847512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	21622795683839236718822094114175889183101475393040731711000027085032991596342	107	UVM_INFO @ 389862233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	71553098121483454258340062858552087942595405346296270486000284495590297834110	107	UVM_INFO @ 46902377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	52492852035342437423063384229241371476327149362653347469124274187402915999689	107	UVM_INFO @ 398528570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	82923679032315286617300420713393751680634808155480687834202614306469766103988	107	UVM_INFO @ 173030440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	2034967423916402465430478246642839998515986353713874062295284533513188333754	107	UVM_INFO @ 393926869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	82351121876916143680315449678346145781408690833439555079785441620274341799503	107	UVM_INFO @ 79258444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	13157780258571756649178941421891669575578246973932513549932150780665849874757	107	UVM_INFO @ 447677267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	85665139688696096293211735935936781577318481747042000173866043629977331773705	107	UVM_INFO @ 195615435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	27625205689742252835946820971733376098495330461713096463666106180299477043020	107	UVM_INFO @ 246593520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	100633964714484681864810213710661481971874152265847065882070672435060311840046	107	UVM_INFO @ 173064389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	36806357410803581120136104407191405705912391124889788235906180137222550480836	107	UVM_INFO @ 44541057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	70557569623786508474489211302468684268497470929206570480809861674599437346103	107	UVM_INFO @ 73766018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	15105921979822525663168612757505821520902087663715629138679793584683412247634	107	UVM_INFO @ 525207984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	40993208898778933928184181328056600004619201961555026628426600057886028661653	107	UVM_INFO @ 176216080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	18402553695004303627910858588407937598035524232002222384217141316158476994017	107	UVM_INFO @ 1132403155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	84553053605234776868568714918506385131105003678314005256698508453430579340985	107	UVM_INFO @ 91427165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	74764002209744708112474320093527969783644814572959575189769716662548361465044	107	UVM_INFO @ 214173708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	64956147208631755980319873735376582415332436669551713228531165391572595946367	107	UVM_INFO @ 196446583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	65453106987858924965123000502201834842104090362121408012922906409259540209009	107	UVM_INFO @ 80797572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	55969056868529853648740188097715935438015249187542580123006365092416364712311	107	UVM_INFO @ 299163045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	80507894794723990802386936218830867967070803875824669829651595479331569636665	107	UVM_INFO @ 122205026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	13826843357664760937209209485341958220632349406481929826449965249141602965525	107	UVM_INFO @ 302659603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	60620944405930361709062489479266631375842122227560592058183777957349605938914	107	UVM_INFO @ 104564430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	66217492613673735557278901715319647818725838328280298931511940797784236590847	107	UVM_INFO @ 69935871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	114348039256144214095639279589659217418305526264253503278336863498394570927409	107	UVM_INFO @ 682919195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	59843336659524639822045237471272590185695952384864857715867375366837517637743	107	UVM_INFO @ 122725105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	47256770139681615473852434169826336472781311136250427904724223730502015373368	134	UVM_INFO @ 14518797065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	106051218686687643201233738952462931938012417339119364579151997001964824926180	107	UVM_INFO @ 170924153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	100648971714314138078429824764136541852466947448183579536370679448628347876055	107	UVM_INFO @ 162661587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	70286540517220589435115263777915836609176525391012532563177310536484097074065	107	UVM_INFO @ 126667076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	95846697864423779813163439437766489365998854103693425664446325000285513048502	107	UVM_INFO @ 50257693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	106169093680140908932178299857542312028718417887436860936711581631250131176547	107	UVM_INFO @ 136457941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	59985993864700174359672589386060710066835107330670048582180018952609044948712	107	UVM_INFO @ 63632896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				12 test runs
	rv_dm_mem_tl_access_resuming	89133730185535297985181834308830467906049059727223380232530016429943553780678	87	UVM_INFO @ 187413336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	90018373749930068442198672864403443016883264512942419366281351132536203690177	92	UVM_INFO @ 1524812580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	107099814778688651687491280242646430226671998914150984077968463862556604638176	87	UVM_INFO @ 406505667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	69341412392808205087313619926720095460805302076527672145580353040646115781624	137	UVM_INFO @ 633745973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	59781333831194052796348082501011594487064440753480000343341022976395888290359	94	UVM_INFO @ 804757419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	39846065142138111648771357169231210299183150872758545273033163873337267760864	89	UVM_INFO @ 505856674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72414386485328658457582157393344545178107781317707284585813152492397277024148	88	UVM_INFO @ 514224750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	53575344396507002855716427659727666400330755233036729212735733650569463056670	88	UVM_INFO @ 198788611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	63918631682028288680188645326209372649708940177495493678909611830268247465588	88	UVM_INFO @ 545740442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	3126544753146541358161848429008940041954645473494857630727731493976463466770	127	UVM_INFO @ 2516322980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	91165065515242622331003840422012619423147845320796700061573318927023221046739	90	UVM_INFO @ 824040646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	99833336519143840872026717172062462079592790889089137866654431253155468117091	129	UVM_INFO @ 2480227769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				11 test runs
	rv_dm_hart_unavail	70085261550507130683323314997730412713474003081482037447902578298100356033717	87	UVM_INFO @ 111106634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	82761793905899096583434351511375233944304645606202063742729828678722080685471	87	UVM_INFO @ 408369452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	107992246668032063629436347080305183120100518796674856233462316301894737852673	87	UVM_INFO @ 241198418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	14317587506362256558741692845636982986606368674221635982985092080687158075456	87	UVM_INFO @ 94332415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	26073588295866440477201802171195720665790072694014030362937243457443980346035	89	UVM_INFO @ 1502520292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	82543077579514891180460610597207497055458043646370350548205031193124910275031	87	UVM_INFO @ 51946352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	101168942658543918059836106742592161886932118517430828711500186027094970047161	91	UVM_INFO @ 131247065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	5462816385861075785156222349406142575241340596337428951384141686674059237246	100	UVM_INFO @ 961583488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	69278255490585561611093376915544791698062247741029139779365078032795008823367	90	UVM_INFO @ 1247527200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	107235095132025575427083274500512891242065056687236807979136959410866479806974	89	UVM_INFO @ 723591287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	27287954418443892390807402186267538786054695784600700772454853596002180832735	89	UVM_INFO @ 1006059292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				10 test runs
	rv_dm_stress_all_with_rand_reset	47945245708051423862284837347982938444538574529321830301104297791055203011492	96	UVM_INFO @ 299110744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	39796377112304061705589157129577326170891919310357402210389594606485854996256	140	UVM_INFO @ 1517501508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	46945478014784902572645858930889842352206397675452052615209944904853701002580	94	UVM_INFO @ 1895094868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	105386173975987982265296629238173502159197801923876341748048178300239963685480	125	UVM_INFO @ 1833491408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	113993299944412852637957630412570004675289937015082692461924652305364032938265	179	UVM_INFO @ 3948669786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	16620434830693237327265902312047583528254671522976789484603900218556240319235	108	UVM_INFO @ 3677518825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	110731563441700005420118087616811435108628379499037966926604928098261849175228	94	UVM_INFO @ 413068490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	58191730938215300104935601690621108238381265412450945616827383892205840128149	96	UVM_INFO @ 734933895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	45442169507297368318606186295632498922233405588978042190673649488038435730565	95	UVM_INFO @ 1530827725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	45104612288847067667682858469632208791032210742094557617433558019988544621843	101	UVM_INFO @ 3875770682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				8 test runs
	rv_dm_jtag_dmi_debug_disabled	17222143248922003329328763576079820489208350207645981471569951907871399291730	87	UVM_INFO @ 625702679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	61859053670269678484323511386791261675698174745290028017698288562666974530620	87	UVM_INFO @ 412233330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	64887905525256513259988238465729588066835350520409488298164122085090341910701	102	UVM_INFO @ 5184484161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	39903979617394761346310573523580724040115360114999151407765408928000690172182	92	UVM_INFO @ 2787558188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	15893270484415930163651406486130833994441092782766009176621896179949065934512	89	UVM_INFO @ 1014187160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	49516683614565767663704981568893116005800455318765299184054443053351980808566	88	UVM_INFO @ 346010600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	104386474504450707509144977278261165964409630241443636125318218082152673090841	92	UVM_INFO @ 4306367917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	96140949666519158909588201518563547888022150999759883534707538487309249779300	110	UVM_INFO @ 1039614204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	rv_dm_stress_all	39144170002241107219704616352571779917283948316142976061496199964286954712026	None
	rv_dm_stress_all	45386093986664453325518239080037411765685513112192080646513287839357085923291	None
	rv_dm_stress_all	69434122233862062397492949026361986864564884451073071804928556277330886192217	None
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	13342542447275001036945973344804086747554243596746878715349253317358013478407	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---