Simulation Results: rv_timer

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 90.45 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
85.83%
V2S
100.00%
V3
45.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 4.000s 1352.065us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 63.276us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 2.000s 16.795us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 4.000s 3342.844us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 58.760us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 17.912us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 2.000s 16.795us 5 5 100.00
rv_timer_csr_aliasing 1.000s 58.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 4.000s 1276.687us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 5.000s 2819.072us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 534.000s 1293016.907us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 534.000s 1293016.907us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 10.000s 6029.736us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 15.361us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 39.933us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 41.138us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 41.138us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 63.276us 1 1 100.00
rv_timer_csr_rw 2.000s 16.795us 5 5 100.00
rv_timer_csr_aliasing 1.000s 58.760us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 44.415us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 63.276us 1 1 100.00
rv_timer_csr_rw 2.000s 16.795us 5 5 100.00
rv_timer_csr_aliasing 1.000s 58.760us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 44.415us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 49.367us 5 5 100.00
rv_timer_tl_intg_err 2.000s 1467.815us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 1467.815us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 3.000s 725.985us 2 10 20.00
max_value 0 10 0.00
rv_timer_max 2.000s 541.789us 0 10 0.00
stress_all_with_rand_reset 16 20 80.00
rv_timer_stress_all_with_rand_reset 66.000s 7501.069us 16 20 80.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 26 test runs
rv_timer_min 90376381415906534206918753768946468504524142124077332263305208623507888181003 84
UVM_INFO @ 725984673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 81985931542415926061066785494958349009308859537021835136075576991076038869703 84
UVM_INFO @ 77733674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 31093755376063165078660584719512029829636624144622180994043941882384727030153 85
UVM_INFO @ 251544336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 70968329368202714557565436043095919204605791127020217756185137613210542834258 84
UVM_INFO @ 160085694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 67828513120056763809689917202192004844999034315851173130874237429697944526148 86
UVM_INFO @ 71751467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 64154672572901736668569544591959399549188423172312496023168017343103467661275 84
UVM_INFO @ 321507236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 96383361963216000205772473671047016708767546896076056378568584332873069746848 85
UVM_INFO @ 717331641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 113117793828402958432142675777044011184039525985273450703751077150072436388822 86
UVM_INFO @ 119261204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 11598382680948011749170231041987861092595788866134280577499526287963441619059 84
UVM_INFO @ 329321929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 47499822548214238329623408894752604110821519885701604514492412714999545009040 84
UVM_INFO @ 532921390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 60686947951879523115147126762693413988478041630820871510557383583304763714015 84
UVM_INFO @ 70326377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 51377457143885087392162927572556650193654910733995261050260967250902976557056 84
UVM_INFO @ 218642039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 16398045452100614424192993674064732550033027895876097325113298794166889604844 84
UVM_INFO @ 241246535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 40661242850310121325910062550113353116360018045126202792121267087238868448343 84
UVM_INFO @ 81734743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 107341325874941700726168028950739979776205056284482322748955664394818620417824 86
UVM_INFO @ 226180378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 68893055539190514518445423772244209290694574428143143243686882905693983687293 85
UVM_INFO @ 104679799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 39972549752643578176399363197572532490643614215423516098690001336517043254255 84
UVM_INFO @ 123591171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 23757341430411064339267823434588464809051874588896330433494614909434479243987 85
UVM_INFO @ 63353503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 35495279076254295586022122690445884534838583937915786461426643917447106644585 86
UVM_INFO @ 670541541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 1064661917208266730874360181145844257459926723462289905313697821551501694791 85
UVM_INFO @ 115469200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 84240260724001535361564087168293222039889117120826000846595316054854544967487 85
UVM_INFO @ 1276687202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 69337128946098832595392802271508953769309581038800399936946257649658969431968 85
UVM_INFO @ 2885728617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 3408924400755065762582728205029408428653158756447973938105394630669178036129 84
UVM_INFO @ 143599604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 37138489024674672508108763724189776496799333287406371260575799432122809330336 87
UVM_INFO @ 275955779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 44398820842103388298774778149539494642218216146261563367698606651879940622753 84
UVM_INFO @ 1147931976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 98475205061733710936170260422091499720725942462631087941014383285167067030998 84
UVM_INFO @ 1558647413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 62289519587484198802418308797073681372557190201204318209480671344358015257492 84
UVM_INFO @ 541788600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 62263880876535901121555901286943345748115466031677964087967068249410212866401 85
UVM_INFO @ 177718674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 68964988035278690272275543904747203099591572477288557311109265955533851636057 84
UVM_INFO @ 345633290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 5195008090953771136040737970881387888216455753887167419817131651566267227683 84
UVM_INFO @ 217011377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 15211872910556819171806031228045903956019881554973132046354962814982485499405 84
UVM_INFO @ 43385185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 20169465450082525585378833290927333937264466465551076694226803900017064770267 84
UVM_INFO @ 613084644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 63129047976525546466920949891702040928797242335855281679260681041640429864677 84
UVM_INFO @ 90352783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 113684856522533468156873207688012760948884763760776476744612843558705198450830 84
UVM_INFO @ 43321555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 75060108857255695658410344507972079538410047598401072924720905238243248665702 84
UVM_INFO @ 168510982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 3 test runs
rv_timer_stress_all_with_rand_reset 27335024825414430681400579975693271206259036231957160879231764704368224491975 88
UVM_INFO @ 25814582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 105682523423315457002170555374036376004462652241851593188215262612037299544134 220
UVM_INFO @ 8395885326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 18528853437569557114891611492723340499363451829943479571110753076432267920805 237
UVM_INFO @ 2437001730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 89565308081915541244392458367915558426589484195142092540947122836943864968214 84
UVM_INFO @ 168443191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
rv_timer_stress_all_with_rand_reset 82818172412889090816325598428138853325187878433677686138170411964767095973517 239
UVM_INFO @ 11567355185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---