Simulation Results: spi_host

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.88 %
  • code
  • 91.30 %
  • assert
  • 96.60 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.90%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 48.000s 1818.892us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 32.902us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 87.321us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 150.769us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 16.692us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 89.472us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 87.321us 5 5 100.00
spi_host_csr_aliasing 2.000s 16.692us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 176.974us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 76.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 23.782us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 4.000s 764.196us 10 10 100.00
spi_host_error_cmd 2.000s 29.540us 10 10 100.00
spi_host_event 130.000s 34551.862us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 7.000s 2302.707us 10 10 100.00
speed 10 10 100.00
spi_host_speed 7.000s 2302.707us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 7.000s 2302.707us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 332.000s 33826.512us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 206.000s 12408.923us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 40.392us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 7.000s 2302.707us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 7.000s 2302.707us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 48.000s 1818.892us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 48.000s 1818.892us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 63.000s 5685.035us 10 10 100.00
spien 10 10 100.00
spi_host_spien 32.000s 2566.140us 10 10 100.00
stall 8 10 80.00
spi_host_status_stall 92.000s 11824.844us 8 10 80.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 3.000s 111.965us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 4.000s 764.196us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 23.559us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 58.898us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 2224.843us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 2224.843us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 32.902us 1 1 100.00
spi_host_csr_rw 2.000s 87.321us 5 5 100.00
spi_host_csr_aliasing 2.000s 16.692us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 33.570us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 32.902us 1 1 100.00
spi_host_csr_rw 2.000s 87.321us 5 5 100.00
spi_host_csr_aliasing 2.000s 16.692us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 33.570us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 1324.450us 25 25 100.00
spi_host_sec_cm 2.000s 69.198us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 1324.450us 25 25 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed 1 test run
spi_host_status_stall 29978959725592432342862001121671415981972409659633042588656009025087244642618 732
UVM_ERROR @ 605006110 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=605006000 ps
UVM_INFO @ 605006110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: * 1 test run
spi_host_status_stall 110109813110749698321295389203414302260926589375856423339119017333693996509178 695
UVM_INFO @ 166128315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---