Simulation Results: sram_ctrl/main

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.85 %
  • code
  • 95.85 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 7.000s 697.014us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 21.552us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 3.000s 24.828us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 191.333us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 33.831us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 374.395us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 3.000s 24.828us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 33.831us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 297.000s 92633.841us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 116.000s 11336.565us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 49.000s 25502.258us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 274.000s 6477.986us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 189.000s 4316.020us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 73.000s 16893.368us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 80.000s 83789.634us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 44.000s 41994.936us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 8.000s 764.034us 8 8 100.00
sram_ctrl_partial_access_b2b 358.000s 154211.724us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 5503.323us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 2641.867us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 3456.317us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 25.000s 8364.684us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 4.000s 363.958us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 376.000s 230059.149us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 16.156us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 138.445us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 138.445us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 21.552us 1 1 100.00
sram_ctrl_csr_rw 3.000s 24.828us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 33.831us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 63.249us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 21.552us 1 1 100.00
sram_ctrl_csr_rw 3.000s 24.828us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 33.831us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 63.249us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.000s 7465.240us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 5111.437us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 2068.967us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 5111.437us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 2068.967us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 25.000s 8364.684us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 25.000s 8364.684us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 3.000s 24.828us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 44.000s 41994.936us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 44.000s 41994.936us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 44.000s 41994.936us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 80.000s 83789.634us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 6.000s 1384.411us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.000s 7465.240us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 9.000s 8341.826us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 697.014us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 697.014us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 44.000s 41994.936us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 5111.437us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 80.000s 83789.634us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 5111.437us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 5111.437us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 7.000s 697.014us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 5111.437us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 64.000s 20900.719us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 94498351648350174326709494214497473022448907592573773804211153206846080881595 86
UVM_INFO @ 5503322879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 87990921422088119152876916591009144013004072258193324862706843270446700541439 86
UVM_INFO @ 2641867339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 25765983561359285158729372808613719480724680207378206265100022844351086463014 86
UVM_INFO @ 694915112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 1059870044059174227996837028455575933605180953363671822458726245754648390650 86
UVM_INFO @ 2638356668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 28108930064112899275986184072887021088175808711759852602167729216151979991268 86
UVM_INFO @ 2264978194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 17657412192135304916012401656831584918811452511086474187668946356751470422196 86
UVM_INFO @ 681009354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 30889016822865341164625751171155222495686586341727614105443188830063123716806 86
UVM_INFO @ 1397494919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 86210113754822500982098871768934445605140287095499379250485365852383798142100 86
UVM_INFO @ 679966206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 88484543207420321576636558452054924678136361332218036562991216532610520028004 86
UVM_INFO @ 2750616217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 96266108894977704775833041235849272390811572032194739593622638403247858056752 86
UVM_INFO @ 1876235721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 17419224432696985952647968503159932188392107066561297356233648554447828488452 86
UVM_INFO @ 691169211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 67225129961627276169428327374144591085641345268593976680792411913366148617089 86
UVM_INFO @ 941579747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 84214330010403650262094661140472589766800291732803115136973697059494564796521 86
UVM_INFO @ 2735209079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 91801433020923319935159047958802228851711953739072680502797082677457288325518 86
UVM_INFO @ 5075834513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 107619845160010141990489916639514049190332866806649172776572856545457193467268 86
UVM_INFO @ 677109196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 482911797379686772635956794141758800277588862128788851642093235115849345072 86
UVM_INFO @ 2643176308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 97555467012873492514476588924035864073485627345247402627099574945466602276325 86
UVM_INFO @ 671564259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 47924729502532179677246412298899180961697003601311107346712515028638683953315 86
UVM_INFO @ 728934277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 115591076388249807140640631579518103573821058469209298795350922883102307168473 86
UVM_INFO @ 712787063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 82053002867701434381120566445812099372943591948724284518030195296271474360170 86
UVM_INFO @ 664587118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 20091287477503854050595126472236757423719333536604085523514389505422086914067 86
UVM_INFO @ 677466239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 52258761338985353518026854648193960592616602814166579421512733695846179680832 86
UVM_INFO @ 3691635810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 94903088426112934205506283767461397292327967649257345162417598382929175068659 86
UVM_INFO @ 3456316870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 10192996834552476779602593879980418098768776331668166677516227377891651906673 86
UVM_INFO @ 1728602504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---