Simulation Results: ac_range_check

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.29 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.58 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
98.11%
V2
97.73%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 52.000s 3305.055us 20 20 100.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 81.000s 3082.303us 19 20 95.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 176.678us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 43.648us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 53.000s 3043.459us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 27.000s 1697.499us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 7.000s 26.087us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 43.648us 5 5 100.00
ac_range_check_csr_aliasing 27.000s 1697.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 325.997us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 36.000s 1370.421us 1 1 100.00
stress_all 8 10 80.00
ac_range_check_stress_all 239.000s 100290.824us 8 10 80.00
alert_test 10 10 100.00
ac_range_check_alert_test 24.000s 31.568us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 13.350us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 8.000s 33.262us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 8.000s 33.262us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 176.678us 1 1 100.00
ac_range_check_csr_rw 3.000s 43.648us 5 5 100.00
ac_range_check_csr_aliasing 27.000s 1697.499us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 357.240us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 176.678us 1 1 100.00
ac_range_check_csr_rw 3.000s 43.648us 5 5 100.00
ac_range_check_csr_aliasing 27.000s 1697.499us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 357.240us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 22.000s 2234.452us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 22.000s 2234.452us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 22.000s 2234.452us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 22.000s 2234.452us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 124.000s 4371.438us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 19.431us 5 5 100.00
ac_range_check_tl_intg_err 13.000s 1586.748us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 381.000s 2540.329us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 44.000s 10848.069us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 2 test runs
ac_range_check_stress_all 70726537902899034127530585428997220141360723285886396845083269803471551880419 13157
UVM_INFO @ 39930734403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 36088189066230061566256835055235170836341667036231529169664114107032906853188 4368
UVM_INFO @ 3082303433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_scoreboard.sv:166) [scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo. 1 test run
ac_range_check_stress_all 78167500521156149664360181321599868052188850313220382556120118113117978224831 26193
UVM_INFO @ 100290824122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---