| V1 |
|
100.00% |
| V2 |
|
88.17% |
| V2S |
|
96.10% |
| V3 |
|
20.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 86.200s | 19309.687us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 12.220s | 142.506us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 7.730s | 364.147us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 331.610s | 40108.727us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 339.920s | 19586.646us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 13.400s | 768.210us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 7.730s | 364.147us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 339.920s | 19586.646us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 349.350s | 6326.013us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 95.590s | 6517.046us | 50 | 50 | 100.00 | |
| entropy | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3521.200s | 481073.820us | 25 | 25 | 100.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 87.010s | 1990.491us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 86.200s | 19309.687us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 76.970s | 1223.110us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 95.910s | 1431.658us | 50 | 50 | 100.00 | |
| ping_timeout | 20 | 50 | 40.00 | |||
| alert_handler_ping_timeout | 571.190s | 34856.239us | 20 | 50 | 40.00 | |
| lpg | 89 | 100 | 89.00 | |||
| alert_handler_lpg | 3600.133s | 0.000us | 42 | 50 | 84.00 | |
| alert_handler_lpg_stub_clk | 3600.148s | 0.000us | 47 | 50 | 94.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| alert_handler_stress_all | 5698.420s | 333400.906us | 50 | 50 | 100.00 | |
| alert_handler_entropy_stress_test | 1 | 20 | 5.00 | |||
| alert_handler_entropy_stress | 41.370s | 4071.869us | 1 | 20 | 5.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 7.470s | 439.649us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.330s | 7.238us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 38.270s | 417.904us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 38.270s | 417.904us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 12.220s | 142.506us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.730s | 364.147us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 339.920s | 19586.646us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 60.410s | 2870.793us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 12.220s | 142.506us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.730s | 364.147us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 339.920s | 19586.646us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 60.410s | 2870.793us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 438.830s | 10292.087us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 438.830s | 10292.087us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 438.830s | 10292.087us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 438.830s | 10292.087us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1287.710s | 230338.995us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 58.660s | 432.829us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 58.660s | 432.829us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 438.830s | 10292.087us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 86.200s | 19309.687us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 86.200s | 19309.687us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 86.200s | 19309.687us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 86.200s | 19309.687us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 87.010s | 1990.491us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 42 | 50 | 84.00 | |||
| alert_handler_lpg | 3600.133s | 0.000us | 42 | 50 | 84.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 87.010s | 1990.491us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3521.200s | 481073.820us | 25 | 25 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3521.200s | 481073.820us | 25 | 25 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 21.830s | 1368.866us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 2 | 10 | 20.00 | |||
| alert_handler_stress_all_with_rand_reset | 323.640s | 76486.794us | 2 | 10 | 20.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 20 test runs | |||
| alert_handler_ping_timeout | 22048288501746483818420692073185342227449506210822791597197878509771624155534 | 102 |
UVM_INFO @ 14558553926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 114379259580977736482640939851545252734782959584875561838144946099566279891520 | 99 |
UVM_INFO @ 6093389359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 93466542404767901718969601966435870348363441389596934461160664729093220595758 | 102 |
UVM_INFO @ 13586248177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 112013739373935753101079592746888784147094636908329857694127919241676132755986 | 139 |
UVM_INFO @ 9664536475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 23713002854107383703500617050772255199871291606857663263591223665027895568851 | 87 |
UVM_INFO @ 4663111381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 29090854120513120705136831964169426585691007794856702526185240898948080132809 | 84 |
UVM_INFO @ 3423351910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 35842307449158057329374263834862035595113749665293166921523077767476904730447 | 105 |
UVM_INFO @ 3488693967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 28865976303609703373777732375764387462424278599527377954731517574356993509345 | 114 |
UVM_INFO @ 4977529620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 55634831696934114301574598602654123030360005998958634360366774569755681278539 | 84 |
UVM_INFO @ 5245568236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 102626498082196175737290202147050629405313250483896937509019428428098556663280 | 109 |
UVM_INFO @ 4921098571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 56499871978110081654704179338223071266194863702141684959069185705656112403117 | 108 |
UVM_INFO @ 4370147792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 61916110721418270444338096217532898511957846471575481110271071095641549991062 | 93 |
UVM_INFO @ 9922166881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 84258079295459462407136331733682334910506102419564666973595538650707338277171 | 98 |
UVM_INFO @ 4233951546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 101768353769745707368989542564177612552261127923122165459012837794118524354948 | 111 |
UVM_INFO @ 3773680455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 40453952015391904642233952209328328608092355201798390909637430889481029106401 | 153 |
UVM_INFO @ 34856239268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80722806549372825280887678775609617767268783495210541092858732487832293211750 | 111 |
UVM_INFO @ 4352968230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 78401333393220961145863793845780720183912456049159045346022643547592076251080 | 120 |
UVM_INFO @ 17111111153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 101917497860917119305701350980363977240130710858621595694312363792086335251180 | 117 |
UVM_INFO @ 12620604082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 25888324108738766439343472903077359937774290539240087867708792683970092902143 | 117 |
UVM_INFO @ 5802124592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 88082876091065834953319773997107403736472643682295124859258461577488542961873 | 108 |
UVM_INFO @ 5946245956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 19 test runs | |||
| alert_handler_entropy_stress | 32854917454173310778571640180491989177287907020856952712059206047751985920212 | 192 |
UVM_INFO @ 1658505681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 51619842084723241600823753393585307280864661647958150025238677102327182830061 | 168 |
UVM_INFO @ 392018255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 102808278891260937345669738366385252916248865020980273751783997644439712079380 | 190 |
UVM_INFO @ 119328488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 56614155204908684858697610987558403228350179148759791676911666267308081391724 | 194 |
UVM_INFO @ 447195296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 7289204305048558908478888345623561070935599319716103356946062157824672122347 | 186 |
UVM_INFO @ 2738320718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 114414066964210333413468045614310296913526811632859380799985627096374442473894 | 204 |
UVM_INFO @ 1303241391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 57049698747160656284153787765636870442856967028250525761863100035292004591733 | 220 |
UVM_INFO @ 391990185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 114704724628718456458592609423482342951393055608966752416892360504033405612577 | 166 |
UVM_INFO @ 293056882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 5428201343023149238962552922392868975583702700686705630189126178802612119765 | 218 |
UVM_INFO @ 4071868702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 13897390517642433610557219057345847232559621325179572575338811533664939404332 | 138 |
UVM_INFO @ 231066849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 115546354181636463474128918580221785431840969033915607012761089575483990954204 | 212 |
UVM_INFO @ 453131984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 60905019304978948651337227078106586405516696532051432209399574923559673345743 | 214 |
UVM_INFO @ 274195739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 60886056230012319192190889507915332565535280622117133869747710759339136136634 | 184 |
UVM_INFO @ 1109800363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 34093739504809219732286692397567821754626749187258060813462613420617073194319 | 154 |
UVM_INFO @ 459390191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 51758307307045882664473876841263991792246342852814024883274314348524626066399 | 200 |
UVM_INFO @ 817258169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 47896726777885314662783271389134623263156372858934381516741489221264023934068 | 124 |
UVM_INFO @ 1792927358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 34730689479246680785740314745803796514777226623913409009422806396619488116549 | 218 |
UVM_INFO @ 70428056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 47781568932195837294620570673342553519494046470483162076778441272685962478136 | 200 |
UVM_INFO @ 518570502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 53895972742471870424134228206186513454617302891274806005029734966364458275230 | 194 |
UVM_INFO @ 134124681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 9 test runs | |||
| alert_handler_ping_timeout | 19311819399775470578321053780532023213736800581373400679849204630925012492875 | 80 |
UVM_INFO @ 295573678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 68484954878604138427341424845055413922274680841671420100716045190539716246325 | 80 |
UVM_INFO @ 384577290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 31249445723912898929083720021175902285540106154154289990888237955065592300928 | 80 |
UVM_INFO @ 661965954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82725676285256919294442656792689985340493213377645054494578281272521914201791 | 80 |
UVM_INFO @ 5067186008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 99986696617514230534655606776238662331165051369182970287852410933570278096497 | 80 |
UVM_INFO @ 315276845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 12977522220622599000200760114238148190442075942225611050823623388860225855800 | 80 |
UVM_INFO @ 2295340709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 95681466201614005871284641375202309103675086424580853127924916201357322122594 | 80 |
UVM_INFO @ 1401403151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 42985731165986186698164325527726869021457026451146283119992103047706860070752 | 80 |
UVM_INFO @ 85850472257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 10713882440997429366513570570741283147112040878173751389362811232181703689580 | 80 |
UVM_INFO @ 632480645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 9 test runs | |||
| alert_handler_lpg_stub_clk | 107689429221707808492373243475582613041992818937467031085320508523284658836529 | None | ||
| alert_handler_lpg | 51472990109986445182317858189148458857203277765266995671346024494302587781522 | None | ||
| alert_handler_lpg | 38763403242559657994145840069533994046072688739262794067418669532118665262080 | None | ||
| alert_handler_lpg_stub_clk | 37745938304778874286680998351454129830346574715724597094473392145229770429205 | None | ||
| alert_handler_lpg | 73889801152297326504350855397836706330978668183794995058655985980947898669637 | None | ||
| alert_handler_lpg | 18597341122964084128625737627292993726809781520914497614544365990855253972106 | None | ||
| alert_handler_lpg | 96418853200178947069051401623445678076360028627182558756656655843940702244748 | None | ||
| alert_handler_lpg_stub_clk | 11275194010167364054827824500668287475600228730824831750361791360646631947460 | None | ||
| alert_handler_lpg | 3143113095580990300117751799819708142997970096155022079221145628229856352530 | None | ||
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 8 test runs | |||
| alert_handler_stress_all_with_rand_reset | 96364693848688850189384881121545175388769967887168027763997022417388504301656 | 139 |
UVM_INFO @ 2000933455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 69384827930416811467251889608182503600294272840459872821241057124352612462924 | 143 |
UVM_INFO @ 2935917516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 56899860871175485703674208008482982146859272719335081581643483673729674557801 | 85 |
UVM_INFO @ 553769868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 76022329029987651944725657953733904951188483001317913468316664399266379335949 | 93 |
UVM_INFO @ 1660796636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 23724686149727493840625690171603844795859017148654645875354369886230794299407 | 127 |
UVM_INFO @ 3446712423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 59500644875047985468868804429668035684655373397147629556308660757724840561435 | 90 |
UVM_INFO @ 611139217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 29674889806880393449298073953515407124838463771491850232316527350420529236978 | 112 |
UVM_INFO @ 1757991632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 4281937798241146160396612282585724623829863727757502661298137247285870210202 | 83 |
UVM_INFO @ 589342391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:343) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) | 1 test run | |||
| alert_handler_ping_timeout | 9105928101623952148934044295500484346944167591075312392955930661553559863715 | 87 |
UVM_INFO @ 793419389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_accum_cnt | 1 test run | |||
| alert_handler_ping_timeout | 92906472889406424030073734867409715407618499259684079257812856325873022629066 | 87 |
UVM_INFO @ 1855135526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_lpg | 41607930875227618919977462925102495535431983524974329629836245662458672518851 | 81 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|