Simulation Results

Simulation Results: clkmgr

26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
83.64 %

code
79.95 %

assert
94.01 %

func
76.96 %

line
91.59 %

branch
94.43 %

cond
88.74 %

toggle
100.00 %

FSM
25.00 %

Validation stages

V1		73.91%
V2		69.23%
V2S		32.38%
V3		5.00%

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	5.290s	280.359us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.200s	17.414us	1	1	100.00
csr_rw				4	5	80.00
	clkmgr_csr_rw	2.580s	126.313us	4	5	80.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	6.260s	367.863us	0	1	0.00
csr_aliasing				0	1	0.00
	clkmgr_csr_aliasing	1.050s	10.391us	0	1	0.00
csr_mem_rw_with_rand_reset				2	5	40.00
	clkmgr_csr_mem_rw_with_rand_reset	2.390s	73.539us	2	5	40.00
regwen_csr_and_corresponding_lockable_csr				4	6	66.67
	clkmgr_csr_rw	2.580s	126.313us	4	5	80.00
	clkmgr_csr_aliasing	1.050s	10.391us	0	1	0.00

81/117 passed

69.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	3.890s	190.227us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	2.840s	122.098us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.520s	47.348us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	5.290s	280.359us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.130s	13.595us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.050s	10.427us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.130s	13.595us	0	10	0.00
stress_all				1	10	10.00
	clkmgr_stress_all	3.380s	140.672us	1	10	10.00
alert_test				10	10	100.00
	clkmgr_alert_test	2.320s	99.595us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	12.630s	786.305us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	12.630s	786.305us	25	25	100.00
tl_d_outstanding_access				5	12	41.67
	clkmgr_csr_hw_reset	1.200s	17.414us	1	1	100.00
	clkmgr_csr_rw	2.580s	126.313us	4	5	80.00
	clkmgr_csr_aliasing	1.050s	10.391us	0	1	0.00
	clkmgr_same_csr_outstanding	1.040s	5.445us	0	5	0.00
tl_d_partial_access				5	12	41.67
	clkmgr_csr_hw_reset	1.200s	17.414us	1	1	100.00
	clkmgr_csr_rw	2.580s	126.313us	4	5	80.00
	clkmgr_csr_aliasing	1.050s	10.391us	0	1	0.00
	clkmgr_same_csr_outstanding	1.040s	5.445us	0	5	0.00

V2S

34/105 passed

32.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	30	6.67
	clkmgr_sec_cm	119.920s	10078.516us	2	5	40.00
	clkmgr_tl_intg_err	2.140s	89.595us	0	25	0.00
shadow_reg_update_error				18	20	90.00
	clkmgr_shadow_reg_errors	2166.060s	200000.000us	18	20	90.00
shadow_reg_read_clear_staged_value				18	20	90.00
	clkmgr_shadow_reg_errors	2166.060s	200000.000us	18	20	90.00
shadow_reg_storage_error				18	20	90.00
	clkmgr_shadow_reg_errors	2166.060s	200000.000us	18	20	90.00
shadowed_reset_glitch				18	20	90.00
	clkmgr_shadow_reg_errors	2166.060s	200000.000us	18	20	90.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.900s	63.970us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	2.140s	89.595us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.130s	13.595us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.050s	10.427us	0	10	0.00
sec_cm_meas_config_shadow				18	20	90.00
	clkmgr_shadow_reg_errors	2166.060s	200000.000us	18	20	90.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	3.700s	258.481us	10	10	100.00
sec_cm_jitter_config_mubi				4	5	80.00
	clkmgr_csr_rw	2.580s	126.313us	4	5	80.00
sec_cm_idle_ctr_redun				2	5	40.00
	clkmgr_sec_cm	119.920s	10078.516us	2	5	40.00
sec_cm_meas_config_regwen				4	5	80.00
	clkmgr_csr_rw	2.580s	126.313us	4	5	80.00
sec_cm_clk_ctrl_config_regwen				4	5	80.00
	clkmgr_csr_rw	2.580s	126.313us	4	5	80.00
prim_count_check				2	5	40.00
	clkmgr_sec_cm	119.920s	10078.516us	2	5	40.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				1	10	10.00
	clkmgr_regwen	1.870s	54.356us	1	10	10.00
stress_all_with_rand_reset				0	10	0.00
	clkmgr_stress_all_with_rand_reset	9.320s	356.179us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				30 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	75405434031431804404420281174813418925673503634793942558638241634383637606380	75	UVM_INFO @ 63970304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	101972081006348645994343983872044419213124775047355603086627248240881323761753	89	UVM_INFO @ 78145716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	104502497233835454081958813025589474147388180291541026691201722436165263183292	82	UVM_INFO @ 16383914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	128589454123569807075050843482589207223209766709967218946544188634714753213	75	UVM_INFO @ 2978245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	89904952071181133712819715260829677722297140418392931956779817043914465739403	82	UVM_INFO @ 8256175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	67220033681792285415870250228819742495565106526319014224278746362238834459170	76	UVM_INFO @ 31778789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	47509493488377071783422859406779427124950731828984445516830535608392910306973	75	UVM_INFO @ 13993112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	86668404157167529903938580842208272510565715381161056823343684570100358254332	78	UVM_INFO @ 3071457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	90226563585795150146812997655995081970957029405257452664850183416222668939507	75	UVM_INFO @ 9907704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	28651442732205924621668615382333364025326251062250332719525199362069747471333	75	UVM_INFO @ 4144937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	76209094876363144877367544459080219293088863113988879517743283062389724772814	78	UVM_INFO @ 18134447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	100436314300505436839425637754102794560175667949948214836185619222128257326274	75	UVM_INFO @ 1917401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	34517988961723063131313199887413190182751542589901390915541094792071822297868	79	UVM_INFO @ 8050149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	115095265191540472786554803008087915605545658381159883755918245698565534887106	106	UVM_INFO @ 120336890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	51375947360451674214796534938506913951169350783970869631331729359400954430335	75	UVM_INFO @ 2838013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	25409700698900639267164272511346457630753216295722199455893329863777313458252	94	UVM_INFO @ 34725247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	88893690778755767989545486462359002740004960315247720659984158187926336971511	75	UVM_INFO @ 4983118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	115223361090232037965824418810750218102951415633646202855792022083088943507456	90	UVM_INFO @ 25774642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	78654270624017934031057321485262224988830716174401561553460230701383999838502	75	UVM_INFO @ 10790162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	39893517444821099248248883664632253674164922800430698879216354901296748933460	75	UVM_INFO @ 10324043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	90906323536195160954032643465518955419324663260764686486076443088027680238010	86	UVM_INFO @ 17906598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	54696449379463509878903921904763484795083445110672511568589791291957295988969	75	UVM_INFO @ 15250731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	66304133333598399777037943819870289313324813922687515404758578176397735039606	75	UVM_INFO @ 2555808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	84957983701242249458514629754706848810289219441013825024852734944948228914787	82	UVM_INFO @ 3143733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	19716869343126832903143632417837283166688068728608482448849413354827382665986	75	UVM_INFO @ 5762649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	10864792998474939968495001634485789390012501864170126973198429173759482819898	89	UVM_INFO @ 12626588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	115158575184220646546577828980000459489239539076236406748404361512989565354696	97	UVM_INFO @ 55747245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	34702911946492906296461353905183477283860375740250200171609494186440650929222	82	UVM_INFO @ 18715016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	115635602959782067740610513191919921366742456987960426478030938113889708715977	82	UVM_INFO @ 6573104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	29136114247054488710678282137788843922796315937406930926960236109008278833234	112	UVM_INFO @ 30133502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				22 test runs
	clkmgr_frequency_timeout	52765950792166886830190400343979994469930745809655687074696936969988841938390	78	UVM_INFO @ 1944833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	56710481198497005550749790998278802886482456437115511795899850418832933233720	79	UVM_INFO @ 17528628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	4653149666089895797494329879889844946018597745171262757251765709843032370094	78	UVM_INFO @ 69835281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	3038493336616455103622842755099420249524033003930504492147252796855414386822	78	UVM_INFO @ 2569007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	97208781571351649392629345203166376031097482971500578785980975434241162707364	79	UVM_INFO @ 4017551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	31088906399362444270998055058868439155377980674224515382863870443103834918169	77	UVM_INFO @ 9804597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	70042425050709081112315812541175128855896457636756089999179641294392045764985	78	UVM_INFO @ 6934286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	95797554180482007151699815023172636245623120398203871547965881769986366523406	78	UVM_INFO @ 6089088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	47590149808758810468671599270019065591128333958892223773923854901659072292311	78	UVM_INFO @ 4679621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	84826282012189538416367607890647013397030120449450578866188122272403829693255	109	UVM_INFO @ 140672000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	99036850003888925593339543954621047008282768394836687641280042973551143891516	78	UVM_INFO @ 10427465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	66575342232960803640820041771541887662994282198456894830949738832617082513315	94	UVM_INFO @ 196261893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	82371956478981454346556974365208947285024176112369449637983242677439501165866	78	UVM_INFO @ 3710937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	56793280734521723935219308716924304335479782772401046080827756846573245929812	95	UVM_INFO @ 31170899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	87858662982681223426718059693146823343525589440646892602849902273922385591394	77	UVM_INFO @ 16894325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	22144528371685775390923066158924785106409807608342941171135419504889823735218	77	UVM_INFO @ 2772045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	86511771512003313789895047549142709958984311187009589126422926629480015954277	79	UVM_INFO @ 122788748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	36056084409486621816479892728943180723616385654242881547764562871864870394142	77	UVM_INFO @ 3708030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	399656390837388316896126064047933910786123523048290821901766091282956607681	79	UVM_INFO @ 6792338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	77594406269444585095842395077700851663733033383514925522791760671631293343013	78	UVM_INFO @ 5349349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	86845697610980163120015931481462991766978649859245410842570288859807518602241	78	UVM_INFO @ 4711557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	78691056842695188320545089570218987803067640015210990885025715591989576743765	79	UVM_INFO @ 61381286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				20 test runs
	clkmgr_csr_aliasing	10922066807529159331481072443213162088576962996368652661714001872043482737942	75	UVM_INFO @ 10390594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	95032206313115465736414336039150825398318839990295578626590673896734007705061	75	UVM_INFO @ 3138419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	83898702249549503945340960476159286084981151037013323778751727163255282119136	89	UVM_INFO @ 9683138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	5094398114524609516425133952231869788561919944020281973194817568925967102690	93	UVM_INFO @ 9225415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	63960813196456733616478666492137278569507621749014215803245852233679522208251	76	UVM_INFO @ 3904982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	43112913265633482862138797832050800640352213442026021646931548235098894053244	75	UVM_INFO @ 6376472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	79218251971163951491946287551240417734808382934373861696489180045760434720585	75	UVM_INFO @ 25043805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	100447908339253568468996534163525133307351137226351012747320706391347206757799	85	UVM_INFO @ 3844700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	34869491338326545614938692508368061121669140491350700397914079982382795390268	75	UVM_INFO @ 15194070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	8093289577823594140850148876153372993135983083695573807690424859205048481932	75	UVM_INFO @ 4011883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	16211635996841392928689700494876773310961759897184994915679376951784110206253	75	UVM_INFO @ 8350863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	75524183025136218072895750804407471719634621592936461631742882171459888888326	75	UVM_INFO @ 21874315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	36684187633789580048790790595347394889500835771710923655373270550183484095188	75	UVM_INFO @ 3365145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	99754562410720704541934112051597908246045750503628694958535916090518825343148	78	UVM_INFO @ 3530215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	57625314863458624610140355248498965961557891003128726283559994691194243775650	75	UVM_INFO @ 34349396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	34030042902700641990972158730491961814506788217130411922280825568978695311297	86	UVM_INFO @ 15817982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	41929036984153754999294960286302375267243229465950361795537150198873951004315	101	UVM_INFO @ 89594843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	76337066412446428249814580927956745647484707639202965910362649021763666169943	75	UVM_INFO @ 14526630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	96875242299141320527048393070974726437330229176947100672774882098385447022713	85	UVM_INFO @ 4224430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	99701825640100470614218444183247991072753252696745353108819633630961963840524	85	UVM_INFO @ 2780912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				17 test runs
	clkmgr_frequency	24551534637455678007293842017934182984113902069844754618270219355478538250038	75	UVM_INFO @ 13537582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	85755055473421003045682737455326434958401407284119654977991388986959638987690	76	UVM_INFO @ 4176025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	35183971649869078814762178684941709014820922463953783916900542533532590006775	75	UVM_INFO @ 23109514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	23073141341852477995708406544823539085775454550180537077422016092400534192849	77	UVM_INFO @ 121154669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	32693809625638617431181812031533789421207916646252122524785621512837244980035	75	UVM_INFO @ 4799911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	86203951676709572049304018671598148571193492998727414945655455581664696569914	75	UVM_INFO @ 6907599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	47981801588846601231801005585454949735705250321121289640884685720484488685893	350	UVM_INFO @ 356179230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	11510487950917074126440057889838012672977199045255407090171088636161617847338	76	UVM_INFO @ 11094495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	53740720098709749881448475635541087948249852779422434282959472450919370674505	75	UVM_INFO @ 11754145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	81104210999302683614252483298163259951279555192716251095382898693784233978563	125	UVM_INFO @ 105887532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	25990966971891590102897316010006167223772579809615412502531230296341111981836	75	UVM_INFO @ 5750412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	85384359483424633954488108794560304102203736776051212234373834392954954709506	75	UVM_INFO @ 15638134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	79357611213473300206258292595052094790166787013534199784935503555997411077372	76	UVM_INFO @ 13594705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	77399991601455616550506204352607279185408574057332685799601118206861444648476	75	UVM_INFO @ 5550068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	69655298678399582978696946840364711186181018764753301156038511864213900773362	75	UVM_INFO @ 15506212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	65372638626623443818826993708835293944746235366258675251715846168544965953557	77	UVM_INFO @ 6018258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	82388644986579296264792535005800034033784251955628882530102506174858292221086	75	UVM_INFO @ 57893953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				5 test runs
	clkmgr_regwen	111859521598245330122195335882299447786894959194495822214141859947865798942960	74	UVM_INFO @ 4221017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	12423024364361084845739024156542406309452928581996247810966558012136931353245	74	UVM_INFO @ 8801851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	4195818397771801654530327240638049370624098098727983852651563881580686459796	74	UVM_INFO @ 4605432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	96374589876486941354928249063970249914549449484893820295700798662802470604532	74	UVM_INFO @ 3207668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	88777510279893357418342551376635867150779348228703390484234506124367768308037	74	UVM_INFO @ 3310803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	32103081611830070186046116845361914522968986812292858613363770418951918297242	75	UVM_INFO @ 15477396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	28152665987642023685418113549888887131580377455047976521807215395231729183583	75	UVM_INFO @ 7642378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	111043320040571915068020436733532123227598843815984453832438716457989210618993	76	UVM_INFO @ 9744523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	110166151379639821354969712864187707475950998823958954870664571098180154336111	75	UVM_INFO @ 3855338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	95566778771679624128585321248965279863772740999359011274108928723261116587320	76	UVM_INFO @ 5445171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				4 test runs
	clkmgr_regwen	98468390773774784499507129896783940621946031350981555081274539665908509023095	74	UVM_INFO @ 2936280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	60459439904869463121394649383080528771267181678708308629562732383337533040203	74	UVM_INFO @ 4191713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	40687594871366878249354797721306118040189694609493829834880742367261421158378	74	UVM_INFO @ 3169134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	18304185874277280713606405094258725187127180258305859002905539782867335319812	74	UVM_INFO @ 8450005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	clkmgr_sec_cm	67854301595637779124561709510670164948668346498186402080297691835787302861276	94	UVM_INFO @ 38927980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	21943422697795309808648587121254853817454383893814591119486252428902690108297	84	UVM_INFO @ 18242643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	clkmgr_shadow_reg_errors	47547190217194142829675587534292166974324209955269110863874027129136379460409	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	93428165539541377972982628170346438202755349997300338522113657121547306638766	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	90964060714864296642310331947521449084682431157026375807133191008051881718297	75	UVM_INFO @ 367863473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				1 test run
	clkmgr_sec_cm	17159759370446621750479956646729185441773469905746044397685889812957937763830	148	UVM_INFO @ 10078515677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---