Simulation Results

Simulation Results: csrng

26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.46 %

code
96.17 %

assert
97.16 %

func
90.04 %

block
98.49 %

line
99.50 %

branch
96.30 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.09%
V2S		99.07%
V3		10.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	6.000s	260.212us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	29.000s	16.486us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	29.000s	17.963us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	40.000s	455.901us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	33.000s	152.892us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	30.000s	64.709us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	29.000s	17.963us	5	5	100.00
	csrng_csr_aliasing	33.000s	152.892us	1	1	100.00

1282/1307 passed

98.09 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	54.000s	3457.946us	500	500	100.00
err				500	500	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
cmds				0	25	0.00
	csrng_cmds	37.000s	402.677us	0	25	0.00
life cycle				0	25	0.00
	csrng_cmds	37.000s	402.677us	0	25	0.00
stress_all				25	25	100.00
	csrng_stress_all	1062.000s	75967.992us	25	25	100.00
intr_test				10	10	100.00
	csrng_intr_test	22.000s	84.115us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	30.000s	35.577us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	24.000s	1251.619us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	24.000s	1251.619us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	29.000s	16.486us	1	1	100.00
	csrng_csr_rw	29.000s	17.963us	5	5	100.00
	csrng_csr_aliasing	33.000s	152.892us	1	1	100.00
	csrng_same_csr_outstanding	4.000s	42.365us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	29.000s	16.486us	1	1	100.00
	csrng_csr_rw	29.000s	17.963us	5	5	100.00
	csrng_csr_aliasing	33.000s	152.892us	1	1	100.00
	csrng_same_csr_outstanding	4.000s	42.365us	5	5	100.00

V2S

1273/1285 passed

99.07 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	5.000s	83.562us	5	5	100.00
	csrng_tl_intg_err	20.000s	2058.739us	25	25	100.00
sec_cm_config_regwen				18	30	60.00
	csrng_regwen	4.000s	1.234us	13	25	52.00
	csrng_csr_rw	29.000s	17.963us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	54.000s	3457.946us	500	500	100.00
sec_cm_intersig_mubi				25	25	100.00
	csrng_stress_all	1062.000s	75967.992us	25	25	100.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
	csrng_sec_cm	5.000s	83.562us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
	csrng_sec_cm	5.000s	83.562us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
	csrng_sec_cm	5.000s	83.562us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
	csrng_sec_cm	5.000s	83.562us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
	csrng_sec_cm	5.000s	83.562us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	54.000s	3457.946us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
sec_cm_constants_lc_gated				25	25	100.00
	csrng_stress_all	1062.000s	75967.992us	25	25	100.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	54.000s	3457.946us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	20.000s	2058.739us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
	csrng_sec_cm	5.000s	83.562us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00
	csrng_sec_cm	5.000s	83.562us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	29.000s	398.081us	200	200	100.00
	csrng_err	30.000s	28.687us	500	500	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				23 test runs
	csrng_cmds	4933950591504068481374706256035335243049043792621675130977120406593410302286	100	UVM_INFO @ 402676761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	90168203646354040865133233825951255720429238941096510125432290646176686888445	100	UVM_INFO @ 86743208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	5429238123561853840196188601444509522098912672139353774175425077819903024643	100	UVM_INFO @ 65301400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	34187082393534345012088837183323895608154295087183930771434867392779410348267	100	UVM_INFO @ 32263467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	93519200732737190923368592203093654662966409209437574907795257775923442814606	100	UVM_INFO @ 10142832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	27969263265736766386269231811550025151980587250195593021690433301876009530381	100	UVM_INFO @ 133866074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	47715098813135899190192832252603495969847686325453320417545055509189620472847	100	UVM_INFO @ 13764177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60103537612962317082191492442540331208714140508123696353627354522602785859026	100	UVM_INFO @ 77706846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	67427682373298745368541726087325705715845182983017681749665581731050493231969	100	UVM_INFO @ 754745996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	44758825704443784159691790827473319273062032812774301540774214075667714277185	100	UVM_INFO @ 116918240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	85127387014313692287985291047529697121382283000992257542357649713711176772467	110	UVM_INFO @ 105431814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	59216793001586069100161268465257225152213762695473734811836557930185489164916	100	UVM_INFO @ 117914596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15604590127034781077116734626673890307509945207643373767705194384975971719747	100	UVM_INFO @ 259875188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	90988116244656196666014734399320372770254258903334241870149271145238392753416	110	UVM_INFO @ 267446434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	103387978805353426397602789841477168399889041150431952426560815013925835946376	110	UVM_INFO @ 651517459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	70672983622283025012360486744491936005962521252403649414003692606717181439279	100	UVM_INFO @ 1545000768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	29998187598304298178933662992820098149262865122996794031392717433682397504642	100	UVM_INFO @ 397094704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48433299990318051308973304077374258394028049586094289227054961018193118415813	100	UVM_INFO @ 190076148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	103455960221388391961015890681786948154114140911812391234442361650861304245288	100	UVM_INFO @ 31668622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	80125589247618232471774268431579351647040417207725496422691115862723177949532	100	UVM_INFO @ 26344400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	13168195895851718220836258455318069623828250825013485018147293902020347659403	100	UVM_INFO @ 151989636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	100434085088703156689414456953233594821989286868637727188762064695868046061786	100	UVM_INFO @ 89247357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	112046733476161141126232824315017062963358162310830046308929252271992657953249	100	UVM_INFO @ 329111733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				9 test runs
	csrng_regwen	41492096168540519586411980935400551216695828408517416308932700896355129568958	99	UVM_INFO @ 1234001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	103260765875301281968893670847043324782599022253640144959738486784738252670772	99	UVM_INFO @ 10164087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	51056647488632910348611016517715698103885293188303038422878863508393605355541	99	UVM_INFO @ 26385068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	37128051465373123861048271262217177213461663243128866321121970396310606611241	99	UVM_INFO @ 3451015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	89962599507009598578838922792713858061680412851621639975764306924472113664322	99	UVM_INFO @ 2900454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	101860845059911234119051182653654371140347700687164453797528796555737524576468	99	UVM_INFO @ 11371120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	60890315431582715218085171521264700127159847789885314340197716506669781664441	99	UVM_INFO @ 1399717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	33675661580560843281324633088989185785752722040231810798392168836089501919947	99	UVM_INFO @ 4812145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	43228728015464200097136960966925317748648379704808065249250286278693571473500	99	UVM_INFO @ 13604400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				4 test runs
	csrng_stress_all_with_rand_reset	32656858595594986085198787100026884268451243320489571361704075680842078755291	None
	csrng_stress_all_with_rand_reset	34930395924202787535710737877092688368351746478255541407259422725963997400418	None
	csrng_stress_all_with_rand_reset	33272784844552389502219473078002622429108068753456060658176283499747872489295	None
	csrng_stress_all_with_rand_reset	1189982322372845208280247575646500264995720388900783152183791680142638722816	None
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				3 test runs
	csrng_stress_all_with_rand_reset	100631519019269937096606854914909382405924254000930274620375334614415646451757	187	UVM_INFO @ 3038394698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	58958083010549794331934311882584905478562212493522552066499347978790921943730	157	UVM_INFO @ 369789447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	108421000380211616278984714484226350089069598691510618847959660371622045854168	115	UVM_INFO @ 171420206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				3 test runs
	csrng_regwen	56812702036681144662977983757863121908528512742969573183931931114822729674875	99	UVM_INFO @ 1363295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	25041629638926429140558630331188362263018359988750659325851290007003172342076	99	UVM_INFO @ 7187955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	86648613940216357939993621933463689737037573531807858090618952346199733978651	99	UVM_INFO @ 2951792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				2 test runs
	csrng_stress_all_with_rand_reset	113321332508773497578406727730454360769136268254063188096604161743405325226493	122	UVM_INFO @ 964861594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	7753492806022500032029034831952509046827056974329428448224327234033132286136	147	UVM_INFO @ 1471426949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				2 test runs
	csrng_cmds	41204502621207703356039919214541337562369976051161494400687559983701194563178	103	UVM_INFO @ 15000878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	54620033389278710232163345976573521387690803447724127938934503418762442753724	103	UVM_INFO @ 109848801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---