Simulation Results: edn/edn0

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.82 %
  • code
  • 93.98 %
  • assert
  • 98.89 %
  • func
  • 58.60 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 84.01 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
73.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 41.550us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 17.207us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 19.091us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 359.741us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 59.398us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 3.000s 25.796us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 19.091us 5 5 100.00
edn_csr_aliasing 2.000s 59.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.000s 174.514us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.000s 174.514us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.000s 174.514us 100 100 100.00
interrupts 20 20 100.00
edn_intr 2.000s 34.843us 20 20 100.00
alerts 200 200 100.00
edn_alert 3.000s 276.605us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 314.417us 100 100 100.00
disable 95 100 95.00
edn_disable 2.000s 17.987us 50 50 100.00
edn_disable_auto_req_mode 11.000s 500.000us 45 50 90.00
stress_all 30 30 100.00
edn_stress_all 9.000s 440.691us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 30.199us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 41.493us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.000s 224.247us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.000s 224.247us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 2.000s 17.207us 1 1 100.00
edn_csr_rw 2.000s 19.091us 5 5 100.00
edn_csr_aliasing 2.000s 59.398us 1 1 100.00
edn_same_csr_outstanding 2.000s 139.543us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 2.000s 17.207us 1 1 100.00
edn_csr_rw 2.000s 19.091us 5 5 100.00
edn_csr_aliasing 2.000s 59.398us 1 1 100.00
edn_same_csr_outstanding 2.000s 139.543us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 10.000s 6662.366us 5 5 100.00
edn_tl_intg_err 4.000s 207.595us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 25.374us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 276.605us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 10.000s 6662.366us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 10.000s 6662.366us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 10.000s 6662.366us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 10.000s 6662.366us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 276.605us 200 200 100.00
edn_sec_cm 10.000s 6662.366us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 276.605us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.000s 207.595us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 22 30 73.33
edn_stress_all_with_rand_reset 101.000s 16699.511us 22 30 73.33

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
edn_stress_all_with_rand_reset 37929459131625759055067480161715425622799404169084541704890571421500543511608 168
UVM_INFO @ 128315880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 16689710863186809542989422247860621969975704577848818429776594058890224470263 219
UVM_INFO @ 2049615858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 65505090901904641956594624763251622280351612924537569753709600076849234943626 179
UVM_INFO @ 685406012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 70151600773337932895876986905536781937115679102591282055215762974538742103688 196
UVM_INFO @ 1790957106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 54234721011711304378207220611732109777656378323270057249360276124517708101822 168
UVM_INFO @ 817548713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 60659646830715445107687045830563964302688950602589089295690873085929813569790 205
UVM_INFO @ 1138921995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 11356674391676507578542318225109459045647184638366967207275177189927820357026 223
UVM_INFO @ 1342433750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 110989841433750187195277517359075015536264822293044678776348364748494211193485 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 8304285998495922096541898669698625903927009568887458405175438848566402190209 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 34536679450824326779736339260814108005430987065796710539983802483262752589903 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 11383203742413885595816285432636513419871000131476791992976469488394509168058 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 74770697870550062286964686752698661493804491367334844469381516003748202084399 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 9999395703302478567954371534528857328537566752230424994488487051117362818394 147
UVM_INFO @ 11810402596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---