Simulation Results

Simulation Results: edn/edn1

26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.36 %

code
95.66 %

assert
98.18 %

func
92.23 %

line
98.48 %

branch
94.59 %

cond
94.77 %

toggle
96.15 %

FSM
94.32 %

Validation stages

V1		100.00%
V2		98.85%
V2S		100.00%
V3		80.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	edn_smoke	1.240s	68.986us	10	10	100.00
csr_hw_reset				1	1	100.00
	edn_csr_hw_reset	0.950s	66.096us	1	1	100.00
csr_rw				5	5	100.00
	edn_csr_rw	1.140s	17.931us	5	5	100.00
csr_bit_bash				1	1	100.00
	edn_csr_bit_bash	4.940s	1896.118us	1	1	100.00
csr_aliasing				1	1	100.00
	edn_csr_aliasing	1.400s	152.586us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	edn_csr_mem_rw_with_rand_reset	1.450s	113.036us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	edn_csr_rw	1.140s	17.931us	5	5	100.00
	edn_csr_aliasing	1.400s	152.586us	1	1	100.00

600/607 passed

98.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				100	100	100.00
	edn_genbits	8.810s	870.684us	100	100	100.00
csrng_commands				100	100	100.00
	edn_genbits	8.810s	870.684us	100	100	100.00
genbits				100	100	100.00
	edn_genbits	8.810s	870.684us	100	100	100.00
interrupts				20	20	100.00
	edn_intr	1.450s	22.188us	20	20	100.00
alerts				200	200	100.00
	edn_alert	1.780s	472.541us	200	200	100.00
errs				100	100	100.00
	edn_err	1.750s	34.986us	100	100	100.00
disable				93	100	93.00
	edn_disable	1.210s	40.503us	50	50	100.00
	edn_disable_auto_req_mode	6.850s	500.000us	43	50	86.00
stress_all				30	30	100.00
	edn_stress_all	5.820s	305.980us	30	30	100.00
intr_test				10	10	100.00
	edn_intr_test	1.150s	13.518us	10	10	100.00
alert_test				10	10	100.00
	edn_alert_test	1.260s	69.502us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	edn_tl_errors	4.490s	133.304us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	edn_tl_errors	4.490s	133.304us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	edn_csr_hw_reset	0.950s	66.096us	1	1	100.00
	edn_csr_rw	1.140s	17.931us	5	5	100.00
	edn_csr_aliasing	1.400s	152.586us	1	1	100.00
	edn_same_csr_outstanding	1.850s	37.744us	5	5	100.00
tl_d_partial_access				12	12	100.00
	edn_csr_hw_reset	0.950s	66.096us	1	1	100.00
	edn_csr_rw	1.140s	17.931us	5	5	100.00
	edn_csr_aliasing	1.400s	152.586us	1	1	100.00
	edn_same_csr_outstanding	1.850s	37.744us	5	5	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	edn_sec_cm	7.550s	2682.727us	5	5	100.00
	edn_tl_intg_err	3.000s	482.495us	25	25	100.00
sec_cm_config_regwen				5	5	100.00
	edn_regwen	1.350s	258.797us	5	5	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	1.780s	472.541us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	7.550s	2682.727us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	7.550s	2682.727us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	7.550s	2682.727us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	7.550s	2682.727us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	1.780s	472.541us	200	200	100.00
	edn_sec_cm	7.550s	2682.727us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	1.780s	472.541us	200	200	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	edn_tl_intg_err	3.000s	482.495us	25	25	100.00

24/30 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				24	30	80.00
	edn_stress_all_with_rand_reset	101.550s	6318.034us	24	30	80.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				5 test runs
	edn_disable_auto_req_mode	97294556429118213050588019506050982875514302277856740446345113683588208357667	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	25626055173374365096259695855393316433336245155520468387525971103228907210488	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	14440116864788739149774621581139686216353532154225110240041855035989845258958	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	74630012031140699712107909629900643192878706687198231810743090150734483518298	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	87349130829725619581812799083463297436618402614285222047132700051387732394329	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				4 test runs
	edn_stress_all_with_rand_reset	720314614953606147080385013683313508497612554959062217364645900088051720826	290	UVM_INFO @ 1561796768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	46968285468428686139212091071206419561099486643988820275069372931245760721714	170	UVM_INFO @ 1041315634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	82309017085802429854016912460696907302918577908370897107689980085817095475561	176	UVM_INFO @ 2095079967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	57716520069473149574355793682143531394035356140112846758625626276432730516235	215	UVM_INFO @ 2409455696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.				2 test runs
	edn_disable_auto_req_mode	41794689592474716085124667505288351935545293764765994720767758739190588588819	88	UVM_INFO @ 62769337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	27711863624426930977987777972311198161618161806942346341349591888503091409119	88	UVM_INFO @ 69613751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred!				1 test run
	edn_stress_all_with_rand_reset	107600069241082227855259466322810262133668032261624020548405032452727985179216	178	UVM_INFO @ 12639874255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit				1 test run
	edn_stress_all_with_rand_reset	112418079659564673632730165860516474299048947284848359432192897680065286295178	133	/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25 csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg" VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 155002300 ps, Illegal state bin il of coverpoint csrng_cmd_cp in covergroup