Simulation Results: gpio

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.99 %
  • code
  • 92.24 %
  • assert
  • 98.73 %
  • func
  • 100.00 %
  • line
  • 99.89 %
  • branch
  • 97.61 %
  • cond
  • 94.53 %
  • toggle
  • 94.19 %
  • FSM
  • 75.00 %
Validation stages
V1
98.11%
V2
93.63%
V2S
86.67%
V3
35.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 40 40 100.00
gpio_smoke 2.130s 206.413us 10 10 100.00
gpio_smoke_no_pullup_pulldown 2.070s 83.673us 10 10 100.00
gpio_smoke_en_cdc_prim 2.290s 359.530us 10 10 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 2.360s 290.225us 10 10 100.00
csr_hw_reset 1 1 100.00
gpio_csr_hw_reset 1.170s 29.776us 1 1 100.00
csr_rw 4 5 80.00
gpio_csr_rw 1.040s 54.646us 4 5 80.00
csr_bit_bash 1 1 100.00
gpio_csr_bit_bash 4.540s 393.312us 1 1 100.00
csr_aliasing 1 1 100.00
gpio_csr_aliasing 1.520s 50.196us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
gpio_csr_mem_rw_with_rand_reset 1.910s 184.264us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 5 6 83.33
gpio_csr_rw 1.040s 54.646us 4 5 80.00
gpio_csr_aliasing 1.520s 50.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 20 20 100.00
gpio_random_dout_din 1.840s 286.925us 10 10 100.00
gpio_random_dout_din_no_pullup_pulldown 1.880s 34.689us 10 10 100.00
out_in_regs_read_write 10 10 100.00
gpio_dout_din_regs_random_rw 1.340s 189.630us 10 10 100.00
gpio_interrupt_programming 10 10 100.00
gpio_intr_rand_pgm 2.050s 206.362us 10 10 100.00
random_interrupt_trigger 10 10 100.00
gpio_rand_intr_trigger 4.540s 166.211us 10 10 100.00
interrupt_and_noise_filter 10 10 100.00
gpio_intr_with_filter_rand_intr_event 3.970s 504.564us 10 10 100.00
noise_filter_stress 10 10 100.00
gpio_filter_stress 22.370s 743.261us 10 10 100.00
regs_long_reads_and_writes 10 10 100.00
gpio_random_long_reg_writes_reg_reads 8.370s 822.427us 10 10 100.00
full_random 10 10 100.00
gpio_full_random 1.570s 218.749us 10 10 100.00
stress_all 3 10 30.00
gpio_stress_all 85.450s 14811.728us 3 10 30.00
alert_test 10 10 100.00
gpio_alert_test 0.920s 166.131us 10 10 100.00
intr_test 10 10 100.00
gpio_intr_test 0.950s 34.060us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
gpio_tl_errors 5.040s 1044.400us 25 25 100.00
tl_d_illegal_access 25 25 100.00
gpio_tl_errors 5.040s 1044.400us 25 25 100.00
tl_d_outstanding_access 9 12 75.00
gpio_csr_rw 1.040s 54.646us 4 5 80.00
gpio_same_csr_outstanding 1.750s 29.295us 3 5 60.00
gpio_csr_aliasing 1.520s 50.196us 1 1 100.00
gpio_csr_hw_reset 1.170s 29.776us 1 1 100.00
tl_d_partial_access 9 12 75.00
gpio_csr_rw 1.040s 54.646us 4 5 80.00
gpio_same_csr_outstanding 1.750s 29.295us 3 5 60.00
gpio_csr_aliasing 1.520s 50.196us 1 1 100.00
gpio_csr_hw_reset 1.170s 29.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 26 30 86.67
gpio_tl_intg_err 3.270s 213.975us 21 25 84.00
gpio_sec_cm 1.370s 92.695us 5 5 100.00
sec_cm_bus_integrity 21 25 84.00
gpio_tl_intg_err 3.270s 213.975us 21 25 84.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 7 10 70.00
gpio_rand_straps 0.890s 12.726us 7 10 70.00
stress_all_with_rand_reset 0 10 0.00
gpio_stress_all_with_rand_reset 20.490s 1981.295us 0 10 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
gpio_inp_prd_cnt 0.910s 21.344us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 10 test runs
gpio_rand_straps 31842870416549321863987809150428052024117839671367146560081049334794421663417 75
UVM_INFO @ 1980697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 98752452738828425285362984308951461079951593582871545707926811917676473604613 591
UVM_INFO @ 23032509214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 30573436927271867868675109633600790590535538985007367091579746600742595546484 1340
UVM_INFO @ 4376513016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 9662887332366041296276474675234816081714448865113298036595994308447107328839 1846
UVM_INFO @ 14811727992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 36967325636341921082298514920359582311057844540430856850926734547030590735532 378
UVM_INFO @ 5246801076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 70608731085269087553251187021219624231533069296297046002316570707653881314474 1310
UVM_INFO @ 3767575002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 83444954568740904600750815733992421209780240796670459340350009928627539256976 75
UVM_INFO @ 5435898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 86635574845935050405526743406328066524660677733165707704138962904822975523566 1774
UVM_INFO @ 60489609688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 106522681154238523464905184626135953396981486750102417011690245470938623742149 2230
UVM_INFO @ 7443332943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 84218714107354233726624083193455647298352037220577086395925723538827668315085 75
UVM_INFO @ 3047085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 7 test runs
gpio_stress_all_with_rand_reset 63707249109263059128547334441899306387824811400957338742830463368727712526196 78
UVM_INFO @ 13881847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 38120705755278477148685314907377507266504665025555628079297157935454839292462 314
UVM_INFO @ 1981295464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 114095558368526178638035848910136951129255763615875051377839077470787040847496 78
UVM_INFO @ 7730175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 108540744322938471384913117612224851455408067065834164604066255611836457139111 211
UVM_INFO @ 936406146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 115591912581273141952338101240356097078854428033999106413925388759272659583234 78
UVM_INFO @ 50368332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 46542086340002911396105654308263069393882415801875672708294399619894224949560 78
UVM_INFO @ 1960139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 42951665055179624447208970629186386461353965982577558914305614941705939002443 123
UVM_INFO @ 146329301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) 3 test runs
gpio_stress_all_with_rand_reset 53005394386159049750849924450962065514238534930817275926640230277166143180649 82
UVM_INFO @ 315712354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 19128338081352255547778357817859609134482681805908324007868751450832699269950 80
UVM_INFO @ 2737588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58623583725979709989742489944718585004128526516153473891215318994768175491489 80
UVM_INFO @ 131155124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 2 test runs
gpio_same_csr_outstanding 22153627704183781897535894120278761814805899588670212170017207442243523533662 79
UVM_INFO @ 29294706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 88219444296779268310322390282481070539151254001747475852726812108347917810978 77
UVM_INFO @ 489482133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: * 2 test runs
gpio_csr_rw 97384750329704931010499217401770712949891809303813686394858983068730918312408 76
UVM_INFO @ 1555638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_tl_intg_err 109152557685414558297552056601087246256316029560892233447838616373538628547436 159
UVM_INFO @ 50526377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: * 2 test runs
gpio_tl_intg_err 915646192696281467738244787898762246229506975540143277907672363080166863856 151
UVM_INFO @ 86125717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_tl_intg_err 28587352214390579279876499464954712488432111956012012670688147641822548090881 153
UVM_INFO @ 241210810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_*.value_* reset value: * 1 test run
gpio_tl_intg_err 77943314364023962394250200148103973680912589814878329658631142803258036078879 197
UVM_INFO @ 72486596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---