Simulation Results: hmac

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.11 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 17.000s 2893.602us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 21.785us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.000s 15.329us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 167.672us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 735.200us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 855.000s 114158.009us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.000s 15.329us 5 5 100.00
hmac_csr_aliasing 3.000s 735.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 156.000s 19698.705us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 125.000s 2792.986us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 305.000s 38932.616us 30 30 100.00
hmac_test_sha384_vectors 631.000s 20435.368us 75 75 100.00
hmac_test_sha512_vectors 668.000s 82054.103us 75 75 100.00
hmac_test_hmac256_vectors 23.000s 541.733us 50 50 100.00
hmac_test_hmac384_vectors 21.000s 1081.654us 60 60 100.00
hmac_test_hmac512_vectors 28.000s 306.193us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 47.000s 4020.005us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 306.000s 8128.741us 10 10 100.00
error 10 10 100.00
hmac_error 149.000s 46813.885us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 126.000s 58694.532us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 17.000s 2893.602us 10 10 100.00
hmac_long_msg 156.000s 19698.705us 10 10 100.00
hmac_back_pressure 125.000s 2792.986us 25 25 100.00
hmac_datapath_stress 306.000s 8128.741us 10 10 100.00
hmac_burst_wr 47.000s 4020.005us 50 50 100.00
hmac_stress_all 1323.000s 109241.912us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 17.000s 2893.602us 10 10 100.00
hmac_long_msg 156.000s 19698.705us 10 10 100.00
hmac_back_pressure 125.000s 2792.986us 25 25 100.00
hmac_datapath_stress 306.000s 8128.741us 10 10 100.00
hmac_wipe_secret 126.000s 58694.532us 10 10 100.00
hmac_test_sha256_vectors 305.000s 38932.616us 30 30 100.00
hmac_test_sha384_vectors 631.000s 20435.368us 75 75 100.00
hmac_test_sha512_vectors 668.000s 82054.103us 75 75 100.00
hmac_test_hmac256_vectors 23.000s 541.733us 50 50 100.00
hmac_test_hmac384_vectors 21.000s 1081.654us 60 60 100.00
hmac_test_hmac512_vectors 28.000s 306.193us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 17.000s 2893.602us 10 10 100.00
hmac_long_msg 156.000s 19698.705us 10 10 100.00
hmac_back_pressure 125.000s 2792.986us 25 25 100.00
hmac_datapath_stress 306.000s 8128.741us 10 10 100.00
hmac_burst_wr 47.000s 4020.005us 50 50 100.00
hmac_error 149.000s 46813.885us 10 10 100.00
hmac_wipe_secret 126.000s 58694.532us 10 10 100.00
hmac_test_sha256_vectors 305.000s 38932.616us 30 30 100.00
hmac_test_sha384_vectors 631.000s 20435.368us 75 75 100.00
hmac_test_sha512_vectors 668.000s 82054.103us 75 75 100.00
hmac_test_hmac256_vectors 23.000s 541.733us 50 50 100.00
hmac_test_hmac384_vectors 21.000s 1081.654us 60 60 100.00
hmac_test_hmac512_vectors 28.000s 306.193us 75 75 100.00
hmac_stress_all 1323.000s 109241.912us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1323.000s 109241.912us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 34.196us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 26.318us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 5.000s 2718.626us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 5.000s 2718.626us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.000s 21.785us 1 1 100.00
hmac_csr_rw 1.000s 15.329us 5 5 100.00
hmac_csr_aliasing 3.000s 735.200us 1 1 100.00
hmac_same_csr_outstanding 3.000s 171.928us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.000s 21.785us 1 1 100.00
hmac_csr_rw 1.000s 15.329us 5 5 100.00
hmac_csr_aliasing 3.000s 735.200us 1 1 100.00
hmac_same_csr_outstanding 3.000s 171.928us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 177.922us 5 5 100.00
hmac_tl_intg_err 6.000s 1034.299us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 6.000s 1034.299us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 17.000s 2893.602us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.000s 148.126us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 445.000s 31196.968us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 281.176us 1 1 100.00