| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| keymgr_dpe_smoke | 72.000s | 16029.461us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.000s | 39.143us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_rw | 2.000s | 32.392us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_bit_bash | 10.000s | 3984.018us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_aliasing | 3.000s | 44.886us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 2.000s | 29.528us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| keymgr_dpe_csr_rw | 2.000s | 32.392us | 5 | 5 | 100.00 | |
| keymgr_dpe_csr_aliasing | 3.000s | 44.886us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 10 | 10 | 100.00 | |||
| keymgr_dpe_intr_test | 2.000s | 10.671us | 10 | 10 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| keymgr_dpe_alert_test | 2.000s | 12.295us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| keymgr_dpe_tl_errors | 5.000s | 156.057us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| keymgr_dpe_tl_errors | 5.000s | 156.057us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.000s | 39.143us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 2.000s | 32.392us | 5 | 5 | 100.00 | |
| keymgr_dpe_csr_aliasing | 3.000s | 44.886us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 3.000s | 163.715us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.000s | 39.143us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 2.000s | 32.392us | 5 | 5 | 100.00 | |
| keymgr_dpe_csr_aliasing | 3.000s | 44.886us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 3.000s | 163.715us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| keymgr_dpe_sec_cm | 9.000s | 2678.707us | 5 | 5 | 100.00 | |
| keymgr_dpe_tl_intg_err | 7.000s | 216.022us | 25 | 25 | 100.00 | |
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 4.000s | 159.529us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 4.000s | 159.529us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 4.000s | 159.529us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 4.000s | 159.529us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 9.000s | 683.063us | 20 | 20 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| keymgr_dpe_sec_cm | 9.000s | 2678.707us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| keymgr_dpe_sec_cm | 9.000s | 2678.707us | 5 | 5 | 100.00 | |