Simulation Results: lc_ctrl/volatile_unlock_disabled

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.74 %
  • code
  • 93.14 %
  • assert
  • 96.54 %
  • func
  • 88.54 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 88.48 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.000s 245.017us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 23.000s 21.285us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 22.000s 18.981us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 23.000s 58.757us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 23.000s 21.066us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 23.000s 33.876us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 22.000s 18.981us 5 5 100.00
lc_ctrl_csr_aliasing 23.000s 21.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 156.971us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 265.737us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 23.000s 40.562us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 667.379us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 24.000s 364.041us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_ctrl_prog_failure 4.000s 667.379us 20 20 100.00
lc_ctrl_errors 24.000s 364.041us 20 20 100.00
lc_ctrl_security_escalation 12.000s 1715.648us 20 20 100.00
lc_ctrl_jtag_state_failure 65.000s 13545.327us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.000s 1369.461us 19 20 95.00
lc_ctrl_jtag_errors 90.000s 20503.142us 20 20 100.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 15.000s 694.858us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 4572.339us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.000s 1369.461us 19 20 95.00
lc_ctrl_jtag_errors 90.000s 20503.142us 20 20 100.00
lc_ctrl_jtag_access 26.000s 976.975us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 30.000s 1767.238us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 14.000s 294.137us 10 10 100.00
lc_ctrl_jtag_csr_rw 9.000s 254.067us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 36.000s 8230.145us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 16.000s 441.315us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 153.530us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 12.000s 55.817us 10 10 100.00
lc_ctrl_jtag_alert_test 21.000s 108.928us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 16.000s 648.122us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 60.898us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 164.000s 12183.694us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 23.000s 26.195us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 478.259us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 478.259us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 23.000s 21.285us 1 1 100.00
lc_ctrl_csr_rw 22.000s 18.981us 5 5 100.00
lc_ctrl_csr_aliasing 23.000s 21.066us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 147.865us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 23.000s 21.285us 1 1 100.00
lc_ctrl_csr_rw 22.000s 18.981us 5 5 100.00
lc_ctrl_csr_aliasing 23.000s 21.066us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 147.865us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 482.066us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 123.569us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 123.569us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 265.737us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_ctrl_sec_cm 4.000s 482.066us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_ctrl_sec_cm 4.000s 482.066us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_ctrl_sec_cm 4.000s 482.066us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_ctrl_sec_cm 4.000s 482.066us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_ctrl_sec_cm 4.000s 482.066us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_ctrl_sec_cm 4.000s 482.066us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_ctrl_sec_cm 4.000s 482.066us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 11.000s 3027.593us 20 20 100.00
lc_ctrl_sec_cm 4.000s 482.066us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 12.000s 1715.648us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 4.000s 156.971us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 4572.339us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.000s 3055.810us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.000s 3055.810us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 13.000s 563.388us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 540.857us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 540.857us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 60.000s 2828.322us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 12442897177445308151617940414313556066261160406850713567398126285952316340057 1569
UVM_INFO @ 25736067001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68144424731778081144322394450220583027942916515249019416069836169738569368088 4778
UVM_INFO @ 9529850099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 94856206986033177013685402461876488921869543729532487534568178851786668528740 6782
UVM_INFO @ 7452653151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43703343825474833751528594726875963262870749278069626096084508211464912618916 3242
UVM_INFO @ 2828322077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14331502744165238915421075128249722351214829809321265077728142923301626385882 672
UVM_INFO @ 2032352306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 102572113666587863607263991946420895901958401781217760257660285924868103519983 8131
UVM_INFO @ 10259302394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 35534005471293073396602698470693854343410706324640622383574471969624222029933 178
UVM_INFO @ 58495815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---