Simulation Results: lc_ctrl/volatile_unlock_enabled

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.60 %
  • code
  • 94.15 %
  • assert
  • 96.83 %
  • func
  • 89.81 %
  • block
  • 97.16 %
  • line
  • 97.69 %
  • branch
  • 92.79 %
  • toggle
  • 88.51 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
98.83%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.000s 186.502us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 39.544us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 14.174us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 140.525us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 103.320us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 20.774us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 14.174us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 103.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 5.000s 181.571us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 9.000s 1406.520us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 45.862us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 808.043us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 12.000s 561.529us 20 20 100.00
security_escalation 135 140 96.43
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_ctrl_prog_failure 4.000s 808.043us 20 20 100.00
lc_ctrl_errors 12.000s 561.529us 20 20 100.00
lc_ctrl_security_escalation 10.000s 1589.576us 20 20 100.00
lc_ctrl_jtag_state_failure 49.000s 21762.901us 18 20 90.00
lc_ctrl_jtag_prog_failure 12.000s 643.757us 18 20 90.00
lc_ctrl_jtag_errors 85.000s 4899.809us 19 20 95.00
jtag_access 207 210 98.57
lc_ctrl_jtag_smoke 9.000s 2172.324us 20 20 100.00
lc_ctrl_jtag_state_post_trans 18.000s 899.491us 20 20 100.00
lc_ctrl_jtag_prog_failure 12.000s 643.757us 18 20 90.00
lc_ctrl_jtag_errors 85.000s 4899.809us 19 20 95.00
lc_ctrl_jtag_access 22.000s 1217.216us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 16.000s 26013.203us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 120.095us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 404.824us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 17.000s 5085.697us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 15.000s 3741.228us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 48.053us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 775.048us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 142.967us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 71.000s 4255.718us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 142.089us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 444.000s 24732.405us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 2.000s 202.635us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 249.685us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 249.685us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 39.544us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.174us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 103.320us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 45.311us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 39.544us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.174us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 103.320us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 45.311us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 3.000s 466.928us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 202.980us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 202.980us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 9.000s 1406.520us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_ctrl_sec_cm 3.000s 466.928us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_ctrl_sec_cm 3.000s 466.928us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_ctrl_sec_cm 3.000s 466.928us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_ctrl_sec_cm 3.000s 466.928us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_ctrl_sec_cm 3.000s 466.928us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_ctrl_sec_cm 3.000s 466.928us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_ctrl_sec_cm 3.000s 466.928us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 8.000s 4042.917us 20 20 100.00
lc_ctrl_sec_cm 3.000s 466.928us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 10.000s 1589.576us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 5.000s 181.571us 20 20 100.00
lc_ctrl_jtag_state_post_trans 18.000s 899.491us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 597.111us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 597.111us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.000s 1429.342us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 1622.591us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 1622.591us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 3602.145s 0.000us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 91604267242510890231920597095844699109394735776585925798828089536115152156101 1764
UVM_INFO @ 12968025255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 115130458490312674775144403436016976631737551508181226926363927844104839985728 188
UVM_INFO @ 2295904392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 59471939212023898852672631110335899067909688831616104809115019914662602614495 1439
UVM_INFO @ 9009194036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82426899806383388528229472078245435145048148445918873656490783413675958331757 1678
UVM_INFO @ 5616024957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 3 test runs
lc_ctrl_jtag_prog_failure 70911309086982560288181218679442678804162459119050850809520841089195431358949 178
UVM_INFO @ 48341148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 11984161015124701217677336743280875334728825097896472830174160028740456360949 177
UVM_INFO @ 309027638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 45595852980658533131723606243531001428802753005183656275961767407689911639213 179
UVM_INFO @ 85201079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 62703996394260645146757217546293205174052047439412903411575410093611938478 177
UVM_INFO @ 47935031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 60264733771350672411400250199729777393294560626495865919620981430966622660658 179
UVM_INFO @ 33625778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
lc_ctrl_stress_all_with_rand_reset 66319081332913738932083768478377559551257360360574198322416355258194460793583 None